recent research on vlsi

The future transistors

• Wei Cao   ORCID: orcid.org/0000-0003-2556-3195 1 ,
• Huiming Bu 2 ,
• Maud Vinet   ORCID: orcid.org/0000-0001-6757-295X 3 ,
• Min Cao 4 ,
• Shinichi Takagi 5 ,
• Sungwoo Hwang   ORCID: orcid.org/0000-0003-0151-791X 6 ,
• Tahir Ghani 7 &
• Kaustav Banerjee   ORCID: orcid.org/0000-0001-5344-0921 1  

Nature volume  620 ,  pages 501–515 ( 2023 ) Cite this article

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• Electrical and electronic engineering
• Electronic devices

A Publisher Correction to this article was published on 05 September 2023

This article has been updated

The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of complementary metal–oxide–semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the knowledge derived from previous scaling efforts, as well as the research efforts needed to make the transistors relevant to future logic integrated-circuit products. We also detail our vision of beyond-MOSFET future transistors and potential innovation opportunities. We anticipate that innovations in transistor technologies will continue to have a central role in driving future materials, device physics and topology, heterogeneous vertical and lateral integration, and computing technologies.

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Change history, 05 september 2023.

A Correction to this paper has been published: https://doi.org/10.1038/s41586-023-06576-6

Fleming, J. Instrument for converting alternating electric currents into continuous currents. US patent 803684A (1905).

Bardeen, J. & Brattain, W. The transistor, a semi-conductor triode. Phys. Rev. 74 , 230–231 (1948). Demonstration of a solid-state transistor .

Lilienfeld, J. E. Method and apparatus for controlling electric currents. US patent 1,745,175 (1930). The original idea of a FET .

Atalla, M. M. et al. Stabilization of silicon surfaces by thermally grown oxides. Bell Syst. Tech. J. 38 , 749–783 (1959). The key enabling innovation responsible for the rise of MOSFETs .

Kahng, D. Electric field controlled semiconductor device. US patent 3,102,230 (1963).

Auth, C. et al. A 10 nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects. In IEEE International Electron Devices Meeting 673–676 (IEEE, 2017).

Dennard, R. et al. Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid State Circuits 9 , 256–268 (1974).

Article   ADS   Google Scholar  

Mistry, K. et al. A 2.0V, 0.35 µm partially depleted SOI-CMOS technology. In IEEE International Electron Devices Meeting 583–586 (IEEE, 1997).

Tenbroek, B. et al. Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques. IEEE Trans. Electron Devices 43 , 2240–2248 (1996).

Ghani, T. et al. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. In IEEE International Electron Devices Meeting 978–980 (IEEE, 2003). Commercialization of strained-silicon technology .

Mistry, K. et al. A 45 nm logic technology with high- k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In IEEE International Electron Devices Meeting 247–250 (IEEE, 2007). Commercialization of high- k + metal-gate CMOS technology .

Auth, C. et al. A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In IEEE VLSI Technology Symposium 131–132 (IEEE, 2012). Commercialization of 3D FinFETs .

Bohr, M., Chau, R., Ghani, T. & Mistry, K. The high- k solution. IEEE Spectr. 44 , 29–35 (2007).

Article   Google Scholar  

Kuhn, K. J. Considerations for ultimate CMOS scaling. IEEE Trans. Electron Devices 59 , 1813–1828 (2012).

Article   ADS   CAS   Google Scholar  

More Moore table. (page 13, Table MM9) International Roadmap for Devices and Systems IRDS 2022 More Moore (ieee.org) (2022).

Luryi, S. Quantum capacitance devices. Appl. Phys. Lett. 52 , 501–503 (1988).

Sze, S. M. & Ng, K. K. Physics of Semiconductor Devices 3rd edn (Wiley-Interscience, 2007).

Asenov, A. Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 µm MOSFET’s: a 3-D atomistic simulation study. IEEE Trans. Electron Devices 45 , 2505–2513 (1998).

Dadgour, H., Endo, K., De, V. & Banerjee, K. Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability. In IEEE International Electron Devices Meeting 705–708 (IEEE, 2008).

Kuhn, K. et al. Process technology variation. IEEE Trans. Electron Devices 58 , 2197–2208 (2011).

Grasser, T. et al. NBTI in nanoscale MOSFETs—the ultimate modeling benchmark. IEEE Trans. Electron Devices 61 , 3586–3593 (2014).

Cartier, E. et al. Fundamental aspects of HfO 2 -based high- k metal gate stack reliability and implications on t inv -scaling. In IEEE International Electron Devices Meeting 441–444 (IEEE, 2011).

Yu, B., Wann, C., Nowak, E. D., Noda, K. & Hu, C. Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFETs. IEEE Trans. Electron Devices 44 , 627–634 (1997).

Welser, J., Hoyt, J. L. & Gibbons, J. F. NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon–germanium structures. In IEEE International Electron Devices Meeting 1000–1002 (IEEE, 1992).

Ota, K. et al. Novel locally strained channel technique for high performance 55 nm CMOS. In IEEE International Electron Devices Meeting 27–30 (IEEE, 2002).

Yeo, Y., Lu, Q., King, T-J. & Hu, C. Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium. In IEEE International Electron Devices Meeting 753–756 (IEEE, 2000).

Takagi, S. et al. III–V/Ge channel MOS device technologies in nano CMOS era. Jpn J. Appl. Phys. 54 , 06FA01 (2015).

del Alamo, J. A. et al. Nanometer-scale III–V MOSFETs. IEEE J. Electon Devices Soc. 4 , 205–214 (2016).

Yeap, G. et al. 5nm CMOS production technology platform featuring full-fledged EUV and high-mobility channel FinFETs with densest 0.021 µm 2 SRAM cells for mobile SoC and high-performance computing applications. In IEEE International Electron Devices Meeting 879–882 (IEEE, 2019).

Skotnicki, T. & Boeuf, F. How can high mobility channel materials boost or degrade performance in advanced CMOS. In IEEE VLSI Technology Symposium 153–154 (IEEE, 2010).

Jin, D., Kim, D., Kim, T. & del Alamo, J. A. Quantum capacitance in scaled down III–V FETs. In IEEE International Electron Devices Meeting 495–498 (IEEE, 2009).

Koba, S. et al. Channel length scaling limits of III–V channel MOSFETs governed by source–drain direct tunneling. Jpn J. Appl. Phys. 53 , 04EC10 (2014).

Article   CAS   Google Scholar  

Zheng, Z. et al. Gallium nitride-based complementary logic integrated circuits. Nat. Electron. 4 , 595–603 (2021).

Yan, R., Ourmazd, A. & Lee, K. Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Devices 39 , 1704–1710 (1992). Provides a simple but important MOSFET scaling guideline .

Frank, D., Taur, Y. & Wong, H. Generalized scale length for two-dimensional effects in MOSFET’s. IEEE Electron Device Lett. 19 , 385–387 (1998).

Ando, T. Ultimate scaling of high- k gate dielectrics: higher- κ or interfacial layer scavenging? Materials 5 , 478–500 (2012).

Article   ADS   CAS   PubMed   PubMed Central   Google Scholar  

Robertson, J. & Wallace, R. M. High- k materials and metal gates for CMOS applications. Mater. Sci. Eng. R 88 , 1–41 (2014).

Hayashi, Y. Gate insulator type field effect transistor. Japanese patent JP1791730 (filed 24 June 1980) (1993). Proposal for a 3D transistor .

Hisamoto, D., Kaga, T., Kawamoto, Y. & Takeda, E. A fully depleted lean-channel transistor (DELTA)—a novel vertical ultrathin SOI MOSFET. In IEEE International Electron Devices Meeting 833–836 (IEEE, 1989).

Hisamoto, D. et al. A folded‐channel MOSFET for deep‐sub‐tenth micron era. In IEEE International Electron Devices Meeting 1032–1034 (IEEE, 1998). A prototype demonstration of an ultrathin-body 3D FinFET .

Huang, X. et al. Sub 50‐nm FinFET: PMOS. In IEEE International Electron Devices Meeting 67–70 (IEEE, 1999).

Rasouli, S., Dadgour, H., Endo, K., Koike, H. & Banerjee, K. Design optimization of FinFET domino logic considering the width quantization property. IEEE Trans. Electon Devices 57 , 2934–2943 (2010).

Kawasaki, H. Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond. In IEEE International Electron Devices Meeting 289–292 (IEEE, 2009).

Niimi, H. et al. Sub-10 −9 Ω-cm 2 n-type contact resistivity for FinFET technology. IEEE Electron Device Lett. 37 , 1371–1374 (2016).

He, X. et al. Impact of aggressive fin width scaling on FinFET device characteristics. In IEEE International Electron Devices Meeting 493–496 (IEEE, 2017).

Appenzeller, J. et al. Toward nanowire electronics. IEEE Trans. Electron Devices 55 , 2827–2845 (2008).

Mizutani, T. et al. Threshold voltage and current variability of extremely narrow silicon nanowire MOSFETs with width down to 2 nm. In Silicon Nanoelectronics Workshop 1–2 (Publishers are Japan Society of Applied Physics, IEEE, 2015).

Mertens, H. et al. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates. In IEEE VLSI Technology Symposium 1–2 (IEEE, 2016).

Yang, B. et al. Vertical silicon-nanowire formation and gate-all-around MOSFET. IEEE Electron Device Lett. 29 , 791–794 (2008).

Loubet, N. et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In IEEE VLSI Technology Symposium 230–231 (IEEE, 2017).

Jagannathan, H. et al. Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices. In IEEE International Electron Devices Meeting 557–560 (IEEE, 2021).

Weckx, P. et al. Novel forksheet device architecture as ultimate logic scaling device towards 2nm. In IEEE International Electron Devices Meeting 36.5.1–36.5.4 (IEEE, 2019).

Wang, R. et al. Experimental study on quasi-ballistic transport in silicon nanowire transistors and the impact of self-heating effects. In IEEE International Electron Devices Meeting 1.4.1–1.4.4 (IEEE, 2008).

Zhuge, J. et al. Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology. In IEEE International Electron Devices Meeting 61–64 (IEEE, 2009).

Iijima, S. & Ichihashi, T. Single-shell carbon nanotubes of 1-nm diameter. Nature 363 , 603–605 (1993).

Novoselov, K. S. et al. Two-dimensional atomic crystals. Proc. Natl Acad. Sci. USA 102 , 10451–10453 (2005).

Ajayan, P., Kim, P. & Banerjee, K. Two-dimensional van der Waals materials. Phys. Today 69 , 38–44 (2016).

Tans, S., Verschueren, A. & Dekker, C. Room-temperature transistor based on a single carbon nanotube. Nature 393 , 49–52 (1998). Demonstration of a carbon nanotube transistor .

Javey, A. et al. High- k dielectrics for advanced carbon nanotube transistors and logic gates. Nat. Mater. 1 , 241–246 (2002).

Article   ADS   CAS   PubMed   Google Scholar  

Wang, Z. et al. Growth and performance of yttrium oxide as an ideal high- k gate dielectric for carbon-based electronics. Nano Lett. 10 , 2024–2030 (2010).

Javey, A., Guo, J., Wang, Q., Lundstrom, M. & Dai, H. Ballistic carbon nanotube field-effect transistors. Nature 424 , 654–657 (2003).

Franklin, A. & Chen, Z. Length scaling of carbon nanotube transistors. Nat. Nanotechnol. 5 , 858–862 (2010).

Qiu, C. et al. Scaling carbon nanotube complementary transistors to 5-nm gate length. Science 355 , 271–276 (2017).

Shabrawy, K., Maharatna, K., Bagnall, D. & Hashimi, B. Modeling SWCNT bandgap and effective mass variation using Monte Carlo approach. IEEE Trans. Nanotechnol . 9 , 184–193 (2010).

Cao, Q. et al. End-bonded contacts for carbon nanotube transistors with low, size-independent resistance. Science 350 , 68–72 (2015).

Cao, Q., Tersoff, J., Farmer, D., Zhu, Y. & Han, S. Carbon nanotube transistors scaled to a 40-nanometer footprint. Science 356 , 1369–1372 (2017). Demonstration of carbon nanotube FETs outperforming state-of-the-art Si MOSFETs .

Jin, S. et al. Using nanoscale thermocapillary flows to create arrays of purely semiconducting single-walled carbon nanotubes. Nat. Nanotechnol. 8 , 347–355 (2013).

Shulaker, M. et al. Carbon nanotube computer. Nature 501 , 526–530 (2013).

Ghosh, S., Bachilo, S. & Weisman, R. Advanced sorting of single-walled carbon nanotubes by nonlinear density-gradient ultracentrifugation. Nat. Nanotechnol. 5 , 443–450 (2010).

Cao, Q. et al. Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics. Nat. Nanotechnol. 8 , 180–186 (2013).

Cao, Q., Han, S. & Tulevski, G. Fringing-field dielectrophoretic assembly of ultrahigh-density semiconducting nanotube arrays with a self-limited pitch. Nat. Commun. 5 , 5071 (2014).

Liu, L. et al. Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics. Science 368 , 850–856 (2020).

Islam, A. Variability and reliability of single-walled carbon nanotube field effect transistors. Electronics 2 , 332–367 (2013).

Novoselov, K. S. et al. Electric field effect in atomically thin carbon films. Science 306 , 666–669 (2004).

Iannaccone, G., Bonaccorso, F., Colombo, L. & Fiori, G. Quantum engineering of transistors based on 2D materials heterostructures. Nat. Nanotechnol. 13 , 138–191 (2018).

Google Scholar  

Li, M., Su, S., Wong, H. & Li, L. How 2D semiconductors could extend Moore’s law? Nature 567 , 169–170 (2019).

Wang, H. et al. Graphene nanoribbons for quantum electronics. Nature Rev. Phys. 3 , 791–802 (2021).

Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS 2 transistors. Nat. Nanotechnol. 6 , 147–150 (2011). Demonstration of a top-gated monolayer 2D semiconductor FET .

Fuhrer, M. & Hone, J. Measurement of mobility in dual-gated MoS 2 transistors. Nat. Nanotechnol. 8 , 146–147 (2013).

Kaasbjerg, K., Thygesen, K. & Jacobsen, K. Phonon-limited mobility in n-type single-layer MoS 2 from first principles. Phys. Rev. B 85 , 115317 (2012).

Liu, W. et al. High-performance few-layer-MoS 2 field-effect-transistor with record low contact-resistance. In IEEE International Electron Devices Meeting 499–502 (IEEE, 2013).

Jena, D. & Konar, A. Enhancement of carrier mobility in semiconductor nanostructures by dielectric engineering. Phys. Rev. Lett. 98 , 136805 (2007).

Article   ADS   PubMed   Google Scholar  

Liu, W. et al. Role of metal contacts in designing high-performance monolayer n-type WSe 2 field effect transistors. Nano Lett. 13 , 1983–1990 (2013). Demonstration of high-performance monolayer 2D-TMD FET .

Fang, H. et al. High-performance single layered WSe 2 p-FETs with chemically doped contacts. Nano Lett. 12 , 3788–3792 (2012).

Das, S., Chen, H., Penumatcha, A. & Appenzeller, J. High performance multilayer MoS 2 transistors with scandium contacts. Nano Lett. 13 , 100–105 (2012).

Kang, J., Liu, W., Sarkar, D., Jena, D. & Banerjee, K. Computational study of metal contacts to monolayer transition-metal dichalcogenide semiconductors. Phys. Rev. X 4 , 031005 (2014). Comprehensive ab initio analysis of metal contacts to 2D semiconductors .

CAS   Google Scholar  

English, C., Shine, G., Dorgan, V., Saraswat, K. & Pop, E. Improved contacts to MoS 2 transistors by ultra-high vacuum metal deposition. Nano Lett. 16 , 3824–3830 (2016).

Kang, J., Sarkar, D., Khatami, Y. & Banerjee, K. Proposal for all-graphene monolithic logic circuits. Appl. Phy. Lett. 103 , 083113 (2013).

Yeh, C., Cao, W., Pal, A., Parto, K. & Banerjee, K. Area-selective-CVD technology enabled top-gated and scalable 2D-heterojunction transistors with dynamically tunable Schottky barrier. In IEEE International Electron Devices Meeting 23.4.1–23.4.4 (IEEE, 2019). Demonstration of single-crystal 2D semiconductor growth in pre-designed sites enabling high-performance FETs .

Kappera, R. et al. Phase-engineered low-resistance contacts for ultrathin MoS 2 transistors. Nat. Mater. 13 , 1128–1134 (2014).

Shen, P. et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature 593 , 211–217 (2021).

O’Brien, K. et al. Advancing 2D monolayer CMOS through contact, channel and interface engineering. In IEEE International Electron Devices Meeting 146–149 (IEEE, 2021).

Chou, A. et al. Antimony semimetal contact with enhanced thermal stability for high performance 2D electronics. In IEEE International Electron Devices Meeting 150–153 (IEEE, 2021)

Li, W. et al. Approaching the quantum limit in two-dimensional semiconductor contacts. Nature 613 , 274–279 (2023).

Cao, W., Chu, J.-H., Parto, K. & Banerjee, K. A mode-balanced reconfigurable logic gate built in a van der Waals strata. npj 2D Mater. Appl. 5 , 20 (2021).

Fang, H. et al. Degenerate n-doping of few-layer transition metal dichalcogenides by potassium. Nano Lett. 13 , 1991–1995 (2013).

Kang, J. et al. On-chip intercalated-graphene inductors for next-generation radio frequency electronics. Nat. Electron. 1 , 46–51 (2018).

Smets, Q. et al. Ultra-scaled MOCVD MoS 2 MOSFETs with 42 nm contact pitch and 250 µA/µm drain current. In IEEE International Electron Devices Meeting 23.4.1–23.4.4 (IEEE, 2019).

Yang, L., Lee, R., Rao, S., Tsai, W. & Ye, P. 10 nm nominal channel length MoS 2 FETs with EOT 2.5 nm and 0.52 mA/µm drain current. Device Research Conference 237−238 (IEEE, 2015).

Li, K. et al. MoS 2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS 2 availability. In IEEE Symposium on VLSI-TSA 52–53 (IEEE, 2016).

Cao, W., Liu, W. & Banerjee, K. Prospects of ultra-thin nanowire gated 2D-FETs for next-generation CMOS technology. In IEEE International Electron Devices Meeting 14.7.1–14.7.4 (IEEE, 2016).

Desai, S. et al. MoS 2 transistor with 1-nanometer gate lengths. Science 354 , 99–102 (2016).

Wu, F. et al. Vertical MoS 2 transistors with sub-1-nm gate lengths. Nature 603 , 259–264 (2022).

Osada, M. & Sasaki, T. Two-dimensional dielectric nanosheets: novel nanoelectronics from nanocrystal building blocks. Adv. Mater. 24 , 210–228 (2012).

Article   CAS   PubMed   Google Scholar  

Chamlagain, B. et al. Thermally oxidized 2D TaS 2 as a high- κ gate dielectric for MoS 2 field-effect transistors. 2D Mater. 4 , 031002 (2017).

Kang, K. et al. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity. Nature 520 , 656–660 (2015). Wafer-scale (4 inch) growth of 2D semiconductor .

Wang, Y. et al. Field-effect transistors made from solution-grown two-dimensional tellurene. Nat. Electron. 1 , 228–236 (2018).

Kang, J., Liu, W. & Banerjee, K. High performance MoS 2 transistors with low resistance molybdenum contacts. Appl. Phys. Lett. 104 , 093106 (2014).

Guo, Y. et al. Study on the resistance distribution at the contact between molybdenum disulfide and metals. ACS Nano 8 , 7771–7779 (2014).

Baugher, B., Churchill, H., Yang, Y. & Jarillo-Herrero, P. Intrinsic electronic transport properties of high-quality monolayer and bilayer MoS 2 . Nano Lett. 13 , 4212–4216 (2013).

Kiriya, D., Tosun, M., Zhao, P., Kang, J. & Javey, A. Air-stable surface charge transfer doping of MoS 2 by benzyl viologen. J. Am. Chem. Soc. 136 , 7853–7856 (2014).

Cui, X. et al. Multi-terminal transport measurements of MoS 2 using a van der Waals heterostructure device platform. Nat. Nanotechnol. 10 , 534–540 (2015).

Li, S. et al. Thickness scaling effect on interfacial barrier and electrical contact to two-dimensional MoS 2 layers. ACS Nano 8 , 12836–12842 (2014).

Allain, A., Kang, J., Banerjee, K. & Kis, A. Electric contacts to two-dimensional semiconductors. Nat. Mater. 14 , 1195–1205 (2015).

Dean, C. R. et al. Boron nitride substrates for high-quality graphene electronics. Nat. Nanotechnol. 5 , 722–726 (2010).

Liu, Y. et al. Pushing the performance limit of sub-100 nm molybdenum disulfide transistors. Nano Lett. 16 , 6337–6342 (2016).

Smithe, K., Suryavanshi, S., Rojo, M., Tedjarati, A. & Pop, E. Low variability in synthetic monolayer MoS 2 devices. ACS Nano 11 , 8456–8463 (2017).

Liu, W., Sarkar, D., Kang, J., Cao, W. & Banerjee, K. Impact of contact on the operation and performance of back-gated monolayer MoS 2 field-effect-transistors. ACS Nano 9 , 7904–7912 (2015).

Zhang, W., Huang, Z., Zhang, W. & Li, Y. Two-dimensional semiconductors with possible high room temperature mobility. Nano Res. 7 , 1731–1737 (2014).

Cui, Y. et al. High-performance monolayer WS 2 field-effect transistors on high- κ dielectrics. Adv. Mater. 27 , 5230–5234 (2015).

Withers, F., Bointon, T. H., Hudson, D. C., Craciun, M. F. & Russo, S. Electron transport of WS 2 transistors in a hexagonal boron nitride dielectric environment. Sci. Rep . 4 , 4967 (2014).

Song, H. S. et al. High-performance top-gated monolayer SnS 2 field-effect transistors and their integrated logic circuits. Nanoscale 5 , 9666–9670 (2013).

Lin, Y. et al. Single-layer ReS 2 : two-dimensional semiconductor with tunable in-plane anisotropy. ACS Nano 9 , 11249–11257 (2015).

Wang, X. et al. Chemical vapor deposition growth of crystalline monolayer MoSe 2 . ACS Nano 8 , 5125–5131 (2014).

Podzorov, V., Gershenson, M. E., Kloc, Ch., Zeis, R. & Bucher, E. High-mobility field-effect transistors based on transition metal dichalcogenides. Appl. Phys. Lett. 84 , 3301–3303 (2004).

Li, S. et al. Halide-assisted atmospheric pressure growth of large WSe 2 and WS 2 monolayer crystals. Appl. Mater. Today 1 , 60–66 (2015).

Pei, T. et al. Few-layer SnSe 2 transistors with high on/off ratios. Appl. Phys. Lett. 108 , 053506 (2016).

Yang, S. et al. Layer-dependent electrical and optoelectronic responses of ReSe 2 nanosheet transistors. Nanoscale 6 , 7226–7231 (2014).

Feng, W., Zheng, W., Cao, W. & Hu, P. Back gated multilayer InSe transistors with enhanced carrier mobilities via the suppression of carrier scattering from a dielectric interface. Adv. Mater. 26 , 6587–6593 (2014).

Zhang, Z. et al. Two-step heating synthesis of sub-3 millimeter-sized orthorhombic black phosphorus single crystal by chemical vapor transport reaction method. Sci. China Mater. 59 , 122–134 (2016).

Li, L. et al. Black phosphorus field-effect transistors. Nat. Nanotechnol. 9 , 372–377 (2014).

Qiao, J., Kong, X., Hu, Z., Yang, F. & Ji, W. High-mobility transport anisotropy and linear dichroism in few-layer black phosphorus. Nat. Commun. 5 , 4475 (2014).

Late, D. J. et al. GaS and GaSe ultrathin layer transistors. Adv. Mater. 24 , 3549–3554 (2012).

Chhowalla, M., Jena, D. & Zhang, H. Two-dimensional semiconductors for transistors. Nat. Rev. Mater. 1 , 16052 (2016).

Singh, J. et al. 14 nm FinFET technology for analog and RF applications. In IEEE VLSI Technology Symposium 140–141 (IEEE, 2017).

Du, Y., Yang, L., Zhou, H. & Ye, P. Performance enhancement of black phosphorus field-effect transistors by chemical doping. IEEE Electron Device Lett. 37 , 429–432 (2016).

Yang, L. et al. Chloride molecular doping technique on 2D materials: WS 2 and MoS 2 . Nano Lett. 14 , 6275–6280 (2014).

Pang, C., Wu, P., Appenzeller, J. & Chen, Z. EOT WS 2 -FET with I DS > 600 µA/µm at V DS = 1V and SS < 70mV/dec at L G = 40 nm. In IEEE International Electron Devices Meeting 3.4.1–3.4.4 (IEEE, 2020).

Cao, W., Kang, J., Sarkar, D., Liu, W. & Banerjee, K. 2D semiconductor FETs- Projections and design for sub-10 nm VLSI. IEEE Trans. Electron Devices 62 , 3459–3469 (2015). A comprehensive scalability analysis of 2D FETs that established the viability of certain 2D semiconductors as optimal channel materials for sub-10-nm FETs .

Liu, L., Kumar, S., Ouyang, Y. & Guo, J. Performance limits of monolayer transition metal dichalcogenide transistors. IEEE Trans. Electron Devices 58 , 3042–3047 (2011).

Liu, R. et al. Integrated digital inverters based on two-dimensional anisotropic ReS 2 field-effect transistors. Nat. Commun. 6 , 6991 (2015).

Mudd, G. et al. Tuning the bandgap of exfoliated InSe nanosheets by quantum confinement. Adv. Mater. 25 , 5714–5718 (2013).

Article   CAS   PubMed   PubMed Central   Google Scholar  

Chau, R. Process and packaging innovations for Moore’s law continuation and beyond. In IEEE International Electron Devices Meeting 1.1.1–1.1.6 (IEEE, 2019).

Salahuddin, S. & Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett . 8 , 405–410 (2008). Proposal of an NC FET .

Ionescu, A. M. et al. Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-MOSFET) with a metal-over-gate architecture In Proceedings International Symposium on Quality Electronic Design 496–501 (IEEE, 2002).

Huang, Q., Huang, R., Pan, Y., Tan, S. & Wang, Y. Resistive-gate field-effect transistor: a novel steep-slope device based on a metal–insulator–metal–oxide gate stack. IEEE Electron Device Lett. 35 , 877–879 (2014).

Han, J., Moon, D. & Meyyappan, M. Nanoscale vacuum channel transistor. Nano Lett. 17 , 2146–2152 (2017).

Shukla, N. et al. A steep-slope transistor based on abrupt electronic phase transition. Nat. Commun. 6 , 7812 (2015).

Gnani, E., Reggiani, S., Gnudi, A. & Baccarani, G. Steep-slope nanowire FET with a superlattice in the source extension. Solid State Electron. 65 – 66 , 108–113 (2011).

Qiu, C. et al. Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches. Science 361 , 387–392 (2018). Demonstration of a Dirac source FET .

Quinn, J., Kawamoto, G. & McCombe, B. Subband spectroscopy by surface channel tunneling. Surf. Sci. 73 , 190–196 (1978). Proposal for a tunnel FET structure using band-to-band tunnelling .

Appenzeller, J., Knoch, Y. & Avouris, P. Band-to-band tunneling in carbon nanotube field-effect transistors. Phys. Rev. Lett . 93 , 196805 (2004).

Wan, J., Zaslavsky, A., Le Royer, C. & Cristoloveanu, S. Novel bipolar-enhanced tunneling FET with simulated high on-current. IEEE Electron Device Lett. 34 , 24–26 (2013).

Saeidi, A. et al. Negative capacitance as performance booster for tunnel FETs and MOSFETs: an experimental study. IEEE Electron Device Lett. 38 , 1485–1488 (2017).

Gopalakrishnan, K., Griffin, P. & Plummer, J. Impact ionization MOS (I-MOS)-part I: device and circuit simulations. IEEE Trans. Electron Devices 52 , 69–76 (2005).

Padilla, A., Chun Wing, Y., Shin, C., Hu, C. & King Liu, T.-J. Feedback FET: a novel transistor exhibiting steep switching behavior at low bias voltages. In IEEE International Electron Devices Meeting 1–4 (IEEE, 2008).

Datta, S. & Das, B. Electronic analog of the electro‐optic modulator. Appl. Phys. Lett. 56 , 665–667 (1990). Proposal of a spin FET .

Manchon, A. et al. New perspectives for Rashba spin–orbital coupling. Nat. Mater. 14 , 871–882 (2015).

Banerjee, S., Register, L., Tutuc, E., Reddy, D. & MacDonald, A. Bilayer pseudospin field-effect transistor (BiSFET): a proposed new logic device. IEEE Electron Device Lett. 30 , 158–160 (2009).

Akarvardar, K. et al. Design considerations for complementary nanoelectro-mechanical logic gates. In IEEE International Electron Devices Meeting 299–302 (IEEE, 2007).

Dadgour, H., Hussain, M., Cassell, A., Singh, N. & Banerjee, K. Impact of scaling on the performance and reliability degradation of metal-contacts in NEMS devices. IEEE International Reliability Physics Symposium 280–289 (IEEE, 2011).

Cao, W., Sarkar, D., Khatami, Y., Kang, J. & Banerjee, K. Subthreshold-swing physics of tunnel field-effect transistors. AIP Adv. 4 , 067141 (2014).

Gandhi, R. et al. CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with ≤50 mV/decade subthreshold swing. IEEE Electron Device Lett. 32 , 1504–1506 (2011).

Tomioka, K., Yoshimura, M. & Fukui, T. Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction. In IEEE Symposium on VLSI Technology 47–48 (IEEE, 2012). A heterojunction tunnel FET with a steep slope .

Knoll, L. et al. Inverters with strained Si nanowire complementary tunnel field-effect transistors. IEEE Electron Device Lett. 34 , 813–815 (2013).

Sarkar, D. et al. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature 526 , 91–95 (2015). A 2D semiconductor channel tunnel FET with a steep slope .

Memisevic. E., Svensson, J., Hellenbrand, M., Lind, E. & Wernersson, L. Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and I on = 10 µA/µm for I off = 1 nA/µm at V DS = 0.3 V. In IEEE International Electron Devices Meeting 500–503 (IEEE, 2016).

Kim, S. et al. Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches. Nat. Nanotechnol. 15 , 203–206 (2020).

Cao, W. et al. Designing band-to-band tunneling field-effect transistors with 2D semiconductors for next-generation low-power VLSI. In IEEE International Electron Devices Meeting 12.3.1–12.3.4 (IEEE, 2015).

Ross, I. M. Semiconductive translating device. US patent 2791760 (1957).

Scott, J. F. & Araujo, C. Ferroelectric memories. Science 246 , 1400–1405 (1989).

Zhou, J. et al. Frequency dependence of performance in Ge negative capacitance PFETs achieving sub-30 mV/decade swing and 110 mV hysteresis. In IEEE International Electron Devices Meeting 373–376 (IEEE, 2017).

Z. Yu, et al. Negative capacitance 2D MoS 2 transistors with sub-60 mV/dec subthreshold swing over 6 orders, 250 µA/µm current density, and nearly-hysteresis-free. In IEEE International Electron Devices Meeting 577–580 (IEEE, 2017).

Si, M. et al. Steep-slope hysteresis-free negative capacitance MoS 2 transistors. Nat. Nanotechnol. 13 , 24–28 (2018).

Lee, M. et al. Ferroelectric Al:HfO 2 negative capacitance FETs. In IEEE International Electron Devices Meeting 565–568 (IEEE, 2017).

Fan, C. et al. Energy-efficient HfAlO x NCFET: using gate strain and defect passivation to realize nearly hysteresis- free sub-25 mV/dec switch with ultralow leakage. In IEEE International Electron Devices Meeting 561–564 (IEEE, 2017).

Chung, W. et al. Hysteresis-free negative capacitance germanium CMOS FinFETs with bi-directional sub-60 mV/dec. In IEEE International Electron Devices Meeting 365–368 (IEEE, 2017).

Cao, W. & Banerjee, K. Is negative capacitance FET a steep-slope logic switch?. Nat. Commun. 11 , 196 (2020). This study demystifies the fundamental limitations of NC FETs and identifies alternative roles of NC in FET design .

Wang, H. et al. New insights into the physical origin of negative capacitance and hysteresis in NCFETs. In IEEE International Electron Devices Meeting 31.1.1–31.1.4 (IEEE, 2018).

Li, X. & Toriumi, A. Direct relationship between sub-60 mV/dec subthreshold swing and internal potential instability in MOSFET externally connected to ferroelectric capacitor. In IEEE International Electron Devices Meeting 31.3.1–31.3.4 (IEEE, 2018).

Jin, C., Jang, K., Saraya, T., Hiramoto, T. & Kobayashi, M. Experimental study on the role of polarization switching in subthreshold characteristics of HfO 2 -based ferroelectric and anti-ferroelectric FET. In IEEE International Electron Devices Meeting 31.5.1–31.5.4 (IEEE, 2018).

Toprasertpong, K., Takenaka, M. & Takagi, S. Direct observation of interface charge behaviors in FeFET by quasi-static split C-V and Hall techniques: revealing FeFET operation. In IEEE International Electron Devices Meeting 23.7.1–23.7.4 (IEEE, 2019).

Su, L. T., Naffziger, S. & Papermaster, M. Multi-chip technologies to unleash computing performance gains over the next decade. In IEEE International Electron Devices Meeting 1–8 (IEEE, 2017).

Huang, C. et al. 3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore’s law scaling. In IEEE International Electron Devices Meeting 20.6.1–20.6.4 (IEEE, 2020).

Banerjee, K., Souri, S., Kapur, P. & Saraswat, K. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc. IEEE 89 , 602–633 (2001). A comprehensive treatise on 3D and heterogeneous integration from a circuit, system, thermal and technology perspective .

Batude, P. et al. Advances in 3D CMOS sequential integration. In IEEE International Electron Devices Meeting 14.1.1–14.1.4 (IEEE, 2009).

Wei, H. et al. Cooling three-dimensional integrated circuits using power delivery networks. In IEEE International Electron Devices Meeting 327–330 (IEEE, 2012).

Jiang, J., Parto, K., Cao, W. & Banerjee, K. Ultimate monolithic-3D integration with 2D materials: rationale, prospects, and challenges. IEEE J. Electron Devices Soc. 7 , 878–887 (2019). A detailed analysis quantifying the benefits of monolithic and heterogeneous 3D integration with 2D materials .

Sachid, A. et al. Monolithic 3D CMOS using layered semiconductors. Adv. Mater. 28 , 2547–2554 (2016).

Jiang, J., Kang, J., Chu, J. & Banerjee, K. All-carbon interconnect scheme integrating graphene-wires and carbon-nanotube-vias. In IEEE International Electron Devices Meeting 342–345 (IEEE, 2017).

Shulaker, M. et al. Monolithic 3D integration of logic and memory: carbon nanotube FETs, resistive RAM, and silicon FETs. In IEEE International Electron Devices Meeting 638–641 (IEEE, 2014).

Zhang, D., Yeh, C., Cao, W. & Banerjee, K. 0.5T0.5R—an ultracompact RRAM cell uniquely enabled by van der Waals heterostructures. IEEE Trans. Electron Devices 68 , 2033–2040 (2021). A novel FET-RRAM hybrid device .

Silver, D. et al. Mastering the game of Go with deep neural networks and tree search. Nature 529 , 484–489 (2016).

Gonzalez-Zalba, M. et al. Scaling silicon-based quantum computing using CMOS technology. Nat. Electron. 4 , 872–884 (2021).

Maurand, R. et al. A CMOS silicon spin qubit. Nat. Commun. 7 , 13575 (2016). Demonstration of a spin qubit based on CMOS technology .

Merolla, P. et al. A million spiking-neuron integrated circuit with a scalable communication network and interface. Science 345 , 668–673 (2014).

Davies, M. et al. Loihi: a neuromorphic manycore processor with on-chip learning. IEEE Micro 38 , 82–99 (2018).

Burd, T. et al. Zen3: the AMD 2nd-generation 7nm x86-64 microprocessor core. In IEEE International Solid-State Circuits Conferenc e 1–3 (IEEE, 2022).

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Acknowledgements

K.B. acknowledges support from the Army Research Office (grant W911NF1810366), the Air Force Office of Scientific Research (grant FA9550-18-1-0448), the Japan Science and Technology Agency CREST Program (grant SB180064) and the National Science Foundation (grant CCF 2132820). K.B. thanks the following individuals for their selfless support during the organization of the collaboration: T. Ernst, CEA-LETI, Grenoble, France; T. Sakurai, The University of Tokyo, Tokyo, Japan; J. Welser, IBM Almaden Research Centre, San Jose, USA. K.B. also thanks S. Oda, Tokyo Institute of Technology, Ōokayama, Japan, for useful discussions.

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VLSI 2020: IBM Research highlights nanosheet, AI processor and photonics advances

At the 2020 Symposia on VLSI Technology and Circuits this week, IBM Research is presenting a variety of papers, short courses, workshops and virtual sessions that demonstrate the latest advances in systems research. Our research spotlights key developments for hybrid cloud infrastructure and AI , marked by improvements in performance, energy efficiency, area scaling, and new workloads.

At VLSI’s first-ever virtual conference, IBM researchers are presenting their work on a universal air spacer compatible with different transistor architectures, whether it’s a fin field-effect transistor (FinFET) or a Nanosheet device architecture. Another team of IBM researchers demonstrates a new AI processor core design resulting in hardware utilization improvements that led to notable enhancements in training efficiency and performance. In a third paper, researchers focused on faster silicon photonics-based network switching, with one goal of eventually making these networks more useful for data centers.

The new air spacer design, taken by a transmission electron microscope.

In their paper, “Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact Over Active Gate (COAG) for Highly Scaled CMOS Technology,” IBM researchers described how the new air spacer reduces effective capacitance – a critical factor impacting the characteristics of CMOS devices – by 15 percent through a reduction in the air spacer’s dielectric constant, leading to performance gains and power reductions at the same time. Although SAC and COAG have been adopted in FinFET technology to reduce the footprint of transistors and standard cells, co-integrating air spacers with SAC and COAG has been challenging.

The spacer is an isolation layer between a gate and the contacts for source and drain in the transistor – essentially, an electronic switch. When the gate is on, electricity flows from the source to the drain, and the gate serves as a valve. The spacer ensures the gate controls only the flow and that the gate and the source and drain are electrically isolated. Without the spacer, the gate cannot serve as a valve.

Researchers positioned their improved air spacer as a viable approach to enhance energy efficiency and performance of advanced CMOS technology by reducing parasitic capacitance, the unwanted capacitance between the parts of an electronic component or circuit due to their proximity to one another.

The paper introduces a new process to form air spacers and provides a practical approach to enabling an electronic device to consume less power while achieving better performance. Excitingly, introducing the new air spacer module into 7nm FinFET produces more performance gains than more costly and disruptive scaling of FinFET to 5nm. The researchers expect their work will help pave the way for their technology’s adoption in FinFET and NanoSheet transistors in the coming years.

Paper authors: Kangguo Cheng, Chanro Park, Heng Wu, Juntao Li, Son Nguyen, Jingyun Zhang, Miaomiao Wang, Sanjay Mehta, Zuoguang Liu,  Richard Conti, Nicolas Loubet, Julien Frougier, Andrew Greene, Tenko Yamashita, Bala Haran, Rama Divakaruni

AI Processor Core

The Digital AI Core with heterogeneous compute engines, featuring dual corelet architecture, shared L1 scratchpad, and memory neighbor interface.

A worldwide team of IBM researchers described a hardware demonstration of a processor core that can be applied to both AI training and inference applications in their paper, “A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.” The researchers achieved leading-edge compute efficiency for robust AI computations via efficient heterogeneous 2-D systolic array-SIMD (single instruction, multiple data) compute engines leveraging compact DLFloat16 Floating Point Units (FPUs). DLFloat is a 16-bit floating point format designed by IBM for deep learning training and inference.

For this study, the researchers optimized a Gen 1 core they first published in 2018, focusing on circuit design, architecture, and software enhancements to produce testchips with Gen 2 cores. This updated Gen 2 design features two corelets working in parallel and sharing memory to facilitate efficient computations. The resulting Gen 2 testchip achieved 5.5x power-efficiency improvements over their Gen 1 testchip for Deep Learning training and inference workflows while using a smaller supply voltage than their first-generation core. Each of the two corelets in the new design has 64 processing elements (each with multiple FPUs) that perform convolution and matrix multiplication operations, which is greater than 80 percent of overall workload in deep learning.

This advancement is part of the Digital AI Core accelerator research in the  IBM Research AI Hardware Center . AI hardware accelerators can be used for building and deploying neural network models  for applications such as speech recognition, natural language processing and computer vision. This latest chip focuses on 16-bit training and inference, but the researchers have also published progress towards   8 bit training  and  inference as low as 2 bits .

Paper authors: Jinwook Oh, SaeKyu Lee, Mingu Kang, Matthew Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce Fleischer, Michael Guillorn, Jungwook Choi, WeiWang, Silvia Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun, Naigang Wang, Fanchieh Yee, Ching Zhou, Vinay Shah, Brian Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang

Silicon Photonics

The silicon photonics switch module.

In the paper, “A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS,” IBM researchers from the U.S. and Canada presented a silicon photonics-based network switch integrated with switching and control electronics. Silicon photonics, an evolving technology in which optical rays transfer data between computer chips, provides an affordable way to build faster switches. Optical rays can carry far more data in less time than electrical conductors.

IBM researchers have created one of the best performing high speed photonic switches, closing the performance gap with packet switching, which the internet uses to send data as well as information about where the data should be delivered. They have also simplified many problems that arise when trying to build electronics and photonics on the same chip. Their goal is to include all of the necessary electronics in order to reduce the packaging load and make a switch that’s both easier to manufacture and more affordable to implement.

The new optical-based circuit switching technology enables switch reconfiguration times of less than 15 nanoseconds while avoiding the high power of more conventional packet-based electronic switches, which require optical-to-electronic domain conversion. The technology uses a scalable process with simple flip chip packaging. Flip chip is a method for interconnecting integrated circuit chips, microelectromechanical systems, or other semiconductor components to external circuitry.

Paper authors: Jonathan E. Proesel, Nicolas Dupuis, Herschel Ainspan, Christian W. Baks, Fuad Doany, Nicolas Boyer, Elaine Cyr, Benjamin G. Lee

Additional Works

Other accepted VLSI papers from IBM and AI Hardware Center members, in addition to those above, include:

“Selective Enablement of Dual Dipoles for Near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies,” R. Bao, K. Watanabe, J. Zhang, H. Zhou, M. Sankarapandian, J. Li, S. Pancharatnam, P. Jamison, R. G Southwick, M. Wang, J. J Demarest, J. Guo, N. Loubet, V. Basker, D. Guo, V. Narayanan, B. Haran, H. Bu, M. Khare

“Si Incorporation Into AsSeGe Chalcogenides for High Thermal Stability, High Endurance and Extremely Low Vth Drift 3D Stackable Cross-point Memory,” H. Y. Cheng, I. T. Kuo, W C. Chien, C. W. Yeh, Y. C. Chou, N. Gong, L. Gignac, C. H. Yang, C. W. Cheng, C. Lavoie, M. Hopstaken, B. R. Bruce, L. Buzi, E. K. Lai, F. Carta, A. Ray, M. H. Lee, H. Y.Ho, W. Kim, M. BrightSky, H. L. Lung

“Structural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices,” S.Mochizuki, B.Colombeau, J.Zhang, S. C.Kung, M.Stolfi, H. Zhou, M. Breton, K. Watanabe, J. Li, H. Jagannathan, M.Cogorno, T.Mandrekar, P.Chen, N. Loubet, S.Natarajan, B.Haran

“Composite Interconnects for High-Performance Computing Beyond the 7nm Node” P. Bhosale, S. Parikh, N. Lanzillo, T. Nogami, R. Tao, M. Gage, R. Shaviv, A. Simon, M. Stolfi, S. Reidy, N.Loubet, B. Haran

“A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM” N. Gong, W. Chien, Y. Chou, C. Yeh, N. Li, H. Cheng, C. Cheng, I. Kuo, C. Yang, R. Bruce, A. Ray, L. Gignac, Y. Lin, C. Miller, T. Perri, W. Kim, L. Buzi, H. Utomo, F. Carta, E. Lai, H. Ho, H. Lung, M. BrightSky

“A 25-50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS” Y. You, G. Wiedemeier, C. Marquart, C. Steffen, E. English, De. Yilma, T. Pham, V. Nammi, J. Okyere, N. Blanchard, A. Sutton, Z. Zhang, D. Friend D. Barba, T. Bohlke, M. Spear, V. Raj, J. Crugnale, D. Dreps, P.A. Francese, M. Kossel, T. Morf

Additionally, at VLSI:

• Alberto Valdes-Garcia will give an invited talk on “Hardware-Software Co-Integration for Configurable 5G mmWave Systems” (Circuits JFS2.1 session)
• Mukta Farooq and Arvind Kumar will offer a short course on “ Heterogenous Integration Architectures for AI ”
• Nicholas Loubet will offer a short course on “ Nanosheet Transistor as a Replacement of FinFET for Future Nodes: Device Advantages & Specific Process Elements ”
• Mounir Meghelli will offer a short course on “ Advances and Trends in High-Speed Serial Links for High-Density IO Applications ”
• Robert Bruce will offer a workshop presentation on “ Designing Material Systems and Algorithms for Analog Computing ”

These advances are part of IBM’s systems research group, which includes initiatives focusing on hybrid cloud, AI hardware, and exploratory science.

• Kangguo Cheng

cmos vlsi Recently Published Documents

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Back propagation neural network based power estimation method for CMOS VLSI circuits

Low power vlsi design techniques: a review.

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

Technologies for creating radiation-resistant VLSI

The technology of radiation-resistant CMOS VLSI is based on industrial IC technology. The design uses feedback circuits and guard rings to compensate for single effects of cosmic particles (SEE). In most critical cases, these influences in digital circuits lead to single faults (SEU), which temporarily disrupt the state of memory cells, to latching (SEL), and in the long term to a catastrophic change of state. Various space programs confirm great prospects for their use in future space structures. The article discusses the effects of using radiation-resistant CMOS technology, technology based on a silicon-on-sapphire structure, CMOS technology on an insulating substrate taking into account typical characteristics, SIMOX-SOI technology, which consists in separation by implantation of oxygen ions. In new designs of circuits, more advanced algorithms should be implemented for the future.

Machine Learning Based Power Estimation for CMOS VLSI Circuits

Abstract The authors have requested that this preprint be withdrawn due to a need to make corrections.

Abstract Nowdays, machine learning (ML) algorithms are receiving massive attention in most of the engineering application since it has capability in complex systems modelling using historical data. Estimation of power for CMOS VLSI circuit using various circuit attributes is proposed using passive machine learning based technique. The proposed method uses supervised learning method which provides a fast and accurate estimation of power without affecting the accuracy of the system. Power estimation using random forest algorithm is relatively new. Accurate estimation of power of CMOS VLSI circuits is estimated by using random forest model which is optimized and tuned by using multi-objective NSGA-II algorithm. It is inferred from the experimental results testing error varies from 1.4 percent to 6.8 percent and in terms of and Mean Square Error is 1.46e-06 in random forest method when compared to BPNN. Statistical estimation like coefficient of determination (𝑅) and Root Mean Square Error (RMSE) are done and it is proven that random Forest is best choice for power estimation of CMOS VLSI circuits with high coefficient of determination of 0.99938. and low RMSE of 0.000116.

Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

Revisiting the Utility of Transmission Gate and Passtransistor Logic Styles in CMOS VLSI Design

Peculiarities of appearance and registration of the latchup in cmos vlsi under uniform pulsed laser irradiation, export citation format, share document.

Emerging VLSI Trends in 2023

• by Maven Silicon
• July 19, 2023
• 3 minutes read

Looking for the latest VLSI trends and VLSI jobs in 2023? Maven Silicon, a leading VLSI training institute, is here to guide you. VLSI is revolutionizing industries with its ability to integrate millions of transistors onto a single chip. In this blog post, we’ll explore the emerging VLSI trends in 2023 that are shaping the future and highlight the exciting job openings in this field. Discover the benefits of pursuing a career in VLSI and how Maven Silicon can help you kick-start your journey.

VLSI Application & Trends in 2023

The applications of VLSI span across various industries, including telecommunications, automotive, healthcare, and artificial intelligence. As we move into 2023, several VLSI trends are making waves:

AI-driven VLSI

Artificial Intelligence (AI) has merged with VLSI, opening up endless possibilities. AI-driven VLSI solutions have gained significant traction in industries like autonomous vehicles, robotics, smart homes, and beyond. The integration of AI algorithms directly into VLSI chips allows for the real-time processing of massive amounts of data, leading to intelligent decision-making and unprecedented levels of efficiency. This trend empowers autonomous vehicles to analyze complex surroundings, robots to navigate dynamically changing environments, and smart homes to adapt to residents’ preferences seamlessly. The synergy between AI and VLSI has propelled us toward a new era of intelligent and responsive technologies.

IoT and VLSI

The Internet of Things (IoT) revolution is in full swing, and VLSI plays a pivotal role in shaping this interconnected ecosystem. Emerging trends in VLSI focus on designing chips optimized for IoT-enabled devices, ensuring efficient data communication, low power consumption, and enhanced security. These specialized VLSI chips enable IoT devices to communicate seamlessly over the internet, exchanging data with other devices and cloud services. Moreover, with advancements in low-power design techniques, IoT devices can operate for extended periods on battery power, making them more practical and environmentally friendly. VLSI’s contribution to IoT is driving the proliferation of smart homes, smart cities, and industrial automation, transforming the way we interact with our surroundings.

Edge Computing and VLSI

Edge computing has emerged as a game-changer in handling real-time data processing and analysis. VLSI’s role in this trend is crucial, as it enables the development of high-performance, energy-efficient chips tailored for edge devices. By processing data locally at the edge, these VLSI chips significantly reduce latency and response times, making them ideal for applications that demand immediate results. Edge devices, such as sensors and cameras, benefit from low-power VLSI solutions that allow for prolonged operation without compromising performance. The combination of edge computing and VLSI has unlocked a new realm of possibilities, from responsive AI applications to smart infrastructure like traffic management and environmental monitoring.

Benefits of VLSI

Exciting and challenging work.

The field of VLSI indeed provides a dynamic and intellectually stimulating work environment for engineers and professionals. As a VLSI engineer, you get the opportunity to be at the forefront of designing complex integrated circuits that power a wide range of electronic devices, from smartphones and computers to IoT devices and automotive electronics.

Also read: Why VLSI is Used?

Lucrative Job Opportunities

The demand for VLSI professionals is on the rise, making it a highly sought-after field with numerous job opportunities across various industries. As technology continues to advance and electronic devices become an integral part of our lives, the need for skilled VLSI engineers has grown significantly.

Positions such as VLSI Design Engineer, Verification Engineer, and Physical Design Engineer are in high demand. VLSI Design Engineers are responsible for designing and architecting integrated circuits, while Verification Engineers focus on validating and testing chip designs. Physical Design Engineers, on the other hand, play a crucial role in implementing the circuit layout to optimize performance and power consumption.

Also read: Skills required to become a VLSI engineer?

Job Openings

If you’re eager to embark on a VLSI career, numerous job openings await you. Maven Silicon is renowned for its VLSI training with 100% placement assistance. Explore exciting roles like VLSI Design Engineer, Verification Engineer, Physical Design Engineer, FPGA Engineer, and Analog/Mixed-Signal Design Engineer.

Also read: Salary of VLSI Engineers in India

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Yes. VLSI is a high growth domain with huge job opportunities. Electronics is the basic knowledge required to get into the VLSI industry. Engineers with Electronics background can enter into VLSI Industry easily. The VLSI Course is helpful for ECE/EEE students to learn and build up the skill set as per the Industry requirement to enter the Chip/IC Design and Verification Domain.

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We help you with support material to enhance your basic knowledge of Digital electronics and perform your best. Our online Digital electronics course will help you to learn and refresh the complete fundamentals of digital electronics, which are highly needed for any VLSI course. Contact us for more details.

We do have online VLSI courses for engineers like you. You can start learning with our hands-on online VLSI courses which comes with labs, project, reference material. We also connect with live Q&A, doubt clarification sessions and Whatsapp support group. Click here to explore and subscribe https://elearn.maven-silicon.com/ . If you are looking for online VLSI course with Placement support, then you refer our Blended VLSI learning program at https://www.maven-silicon.com/blended-vlsi-design-asic-verification

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Steps involved in Chip design Chip’s architecture: Create circuit designs, Run simulations, Supervise layout, Tape out the chip to the foundry and Evaluate the prototype once the chip comes back from the laboratory. Chip designers work to make faster, cheaper and more innovative chips that can automate parts or the entire function of electronic devices. A chip design engineer’s job involves architecture, logic design, circuit design and physical design of the chip, testing, and verification of the final product.

We do have online VLSI courses for engineers like you. You can start learning with our hands-on online VLSI courses which comes with labs, project, reference material. We also connect with live Q&A, doubt clarification sessions and Whatsapp support group. Click here to explore and subscribe https://elearn.maven-silicon.com/ . If you are looking for online VLSI course with Placement support, then you refer our Blended VLSI learning program at https://www.maven-silicon.com/blended-vlsi-design-asic-verification

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Special issue: 26th international symposium on VLSI design and test 2022

• Published: 08 September 2023
• Volume 116 , pages 1–3, ( 2023 )

Cite this article

• Ambika Prasad Shah 1 &
• Sudeb Dasgupta 2  

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1 Introduction

The increasing versatility, performance, compactness and power efficiency of today’s electronic systems is achieved by pushing technology to its physical limits; systems are increasing in size and complexity, comprising thousands of subsystems made of billions of devices. The devices themselves have become smaller and smaller and have reached the atomic scale.

This Special Issue aimed at continuing the discussion about the research activities and related findings carried out the 26th International Symposium on VLSI Design and Test (VDAT-2022) held in Jammu, India, July 17- 19th 2022 with the theme of “Chips to Startup for sustainable development”. Therefore, this Special Issue focuses on the following areas:

Emerging Devices and Material Technologies.

VLSI Circuit and System Design.

IC Reliability, Security and Quality.

CAD for VLSI, Testing and Verification.

FPGA based Design and Embedded Systems.

2 Topics of the special issue

This special issue comprises 7 articles selected after a rigorous review process of the extended versions of papers presented at VDAT-2022. Accepted articles covers various aspects of microelectronics devices, ADC, in-memory computation, reliability and security in integrated circuits, various architectures and devices, and focusing at different levels of abstraction from device level to system level.

Paper “Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing” by Kavita Monga et al. [ 1 ] address the two major issues with the in-memory computation. For precise operation, the applied input signals must be stable and during the input signal generation is the deviation in the width values due to process, voltage, and temperature variations. Authors have proposed to design a tunable delay line that provides a linear PWM signal corresponding to an input vector which is further utilized to perform local computation in memory.

Paper “Cadmium sulfide deposition suited for photo pattern-based SAW device” by Rahul Sharma et al. [ 2 ] demonstrates a surface acoustic wave (SAW) device based on photopatterned interdigital transducer (IDT) created on a cadmium sulfide layer deposited over a lithium niobate substrate using two methods, viz. chemical bath deposition (CBD) and spin-coating. I–V characteristics are measured for photo pattern-based SAW devices with different electrode separation widths.

Paper “Design of a high precision CMOS programmable gain and data rate delta sigma ADC” by Mohd Asim Saeed et al. [ 3 ] presents a general purpose high precision Delta Sigma (ΔΣ) ADC with a common mode rejection of 100 dB, developed for data acquisition of sensors used in a satellite launch vehicle telemetry system. The ADC is also equipped with on chip offset and gain calibration features to reduce the offset and gain errors.

Paper “Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications” by Arvind Bisht et al. [ 4 ] proposes an optimized Nanosheet Transistor (NSHT) with an inner high-k spacer and an underlap region. A symmetric dual-k spacer structure and an undoped underlap region are incorporated into the baseline device to optimize it for better performance. The analog performance of the optimized NSHT is compared with the performance of the baseline NSHT device across the design space.

Paper “A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issues” by Subrata Das et al. [ 5 ] propose an algorithm for the routing of Graphene nanoribbon based interconnect considering minimization of grid area and improvement of interconnect-reliability as the optimization goals with minimum increase in interconnect resistance and delay.

Paper “BTI resilient TG-based high-performance ring oscillator for PUF design” by Shubhang Srivastava et al. [ 6 ] propose a new energy-efficient and aging resilient inverter and ring oscillator based on an aging resilient inverter design. The proposed inverter is 22.57% less power-consuming and 16% faster than the conventional Aging Resilient inverter while showing nearly identical aging characteristics without significant increment in area overhead. Authors also designed ring oscillator from the proposed inverter shows nearly 1.5% higher frequency than the conventional aging resilient ring oscillator for the same number of inverter stages.

Paper “Efficient hardware implementations of Lopez–Dahab projective co-ordinate based scalar multiplication of ECC” by M. Mohamed Asan Basiri [ 7 ] proposes efficient hardware implementations scalar multiplication of Lopez–Dahab projective co-ordinate based ECC in the platforms of application specific integrated circuit (ASIC) and field programmable gate array logic (FPGA). Due to this dual core implementation in FPGA, the throughput of the proposed scalar multiplication in FPGA is greater than various existing designs.

3 Conclusion

All of the papers selected for this Special Issue represent world-leading current research into robust and novel devices, reliability-aware design and hardware security approaches for computing systems and provide interesting and valuable insights into current and future trends and issues within these areas. We hope you will enjoy reading the papers and find them a source of inspiration for your own work.

Monga, K., Shenoy, M. V., Chaturvedi, N., et al. (2023). Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02169-5 .

Article   Google Scholar  

Sharma, R., & Nemade, H. B. (2023). Cadmium sulfide deposition suited for photo pattern-based SAW device. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02172-w .

Saeed, M. A., Srivastava, R. K., Sehgal, D., et al. (2023). Design of a high precision CMOS programmable gain and data rate delta sigma ADC. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02165-9 .

Bisht, A., Pundir, Y. P., & Pal, P. K. (2023). Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02171-x .

Das, S., Das, D. K., & Pandit, S. (2023). A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issues. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02170-y .

Srivastava, S., Verma, A., & Shah, A. P. (2023). BTI resilient TG-based high-performance ring oscillator for PUF design. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02180-w .

M. Mohamed Asan, Basiri Efficient hardware implementations of Lopez–Dahab projective co-ordinate based scalar multiplication of ECC. Analog Integrated Circuits and Signal Processing . https://doi.org/10.1007/s10470-023-02179-3

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Acknowledgements

We sincerely thank all the reviewers for helping us in reviewing the papers in time. We also thank all the staff members of Analog Integrated Circuits and Signal Processing journal for their effortless support. Last but not the least we thank the Editor-in-Chief and handling editor for their help and support throughout the entire process.

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Shah, A.P., Dasgupta, S. Special issue: 26th international symposium on VLSI design and test 2022. Analog Integr Circ Sig Process 116 , 1–3 (2023). https://doi.org/10.1007/s10470-023-02184-6

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If we narrow down our discussion to research in areas like electronics, electrical, computer science, artificial intelligence , wireless communication and related fields, which are the base of everything in this high-tech world. In these fields researchers have developed applications (aided with technology) for every field ranging from biomedical to aerospace and construction, which were nowhere related to electronics or even current.

As the research fields we are talking about are providing base to the developing world and providing it with reliable technologies which are being used in real time, the work of researcher becomes more wide starting with an idea to the realization of the idea in the real world in form of application or product.

To make a reliable and working model the idea of the VLSI design project ( i.e speech processing application, biomedical monitoring system etc) needs to be implemented and re-implemented, re-tested and improvised. The there are many development cycles and techniques available which eases up the implementation like:

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Behavioral simulation is used at initial phase and it is not appropriate for testing the real time behavior of the system in actual environment as it is more close to systems behavior in ideal environment.

We can simulate the actual environment by using different software models (more like software models of channels used to test communication systems) but its capabilities are also limited to human capability to model the environmental conditions in mathematical equations and models.

All of us are familiar with ASIC, their high performance and hardwired implementation. These are good for final implementation but not for intermediate stages of implementation and testing. Nothing is better than ASIC for real time testing of analog  VLSI  circuits. But for digital circuits and DSP applications we have a better option of FPGA (Field Programmable Gate Array).

The hardware co-simulation is a good idea to test and monitor systems in real time. To get more details about  PhD thesis  in VLSI you can do online research or contact us.

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VLSI Design and Technology: Current Research and Future Trends

VLSI Design and Technology is a rapidly evolving field of electrical engineering that deals with the design, fabrication and testing of very large scale integrated circuits. VLSI is an acronym that stands for Very Large Scale Integration and refers to the integration of thousands or even millions of transistors and other components into a single integrated circuit. The development of VLSI has had a profound impact on modern electronics and has been instrumental in enabling the growth of the computer, telecommunications, and consumer electronics industries.

Current Research Areas in VLSI Design and Technology

• Circuit Design: Researchers in this area are focused on developing new and innovative approaches for designing VLSI circuits that are smaller, faster, and consume less power. They are working on new circuit design techniques that can improve the performance, reduce the power consumption, and increase the reliability of VLSI circuits.
• Semiconductor Fabrication: This area of research focuses on improving the fabrication process for VLSI circuits, with the aim of producing high-quality integrated circuits that are smaller, faster, and consume less power. Researchers are working on new fabrication techniques that can improve the uniformity and reliability of VLSI circuits, and reduce the cost of fabrication.
• Circuit Performance: Researchers in this area are working on developing new techniques for evaluating and optimizing the performance of VLSI circuits. They are investigating new methods for measuring the speed, power consumption, and reliability of VLSI circuits, and developing new techniques for improving these parameters.
• Power Management: Power consumption is a critical issue in VLSI design and technology, and researchers in this area are working on developing new techniques for reducing the power consumption of VLSI circuits. They are investigating new approaches for optimizing the power usage of VLSI circuits, and developing new techniques for managing the power consumption of VLSI circuits.
• Reliability Engineering: Reliability is a critical issue in VLSI design and technology, and researchers in this area are working on developing new techniques for improving the reliability of VLSI circuits. They are investigating new approaches for improving the reliability of VLSI circuits, and developing new techniques for predicting and mitigating the effects of failures in VLSI circuits.

Emerging Technologies in VLSI Design and Technology

The field of VLSI design and technology is constantly evolving, and there are many emerging technologies that are likely to have a significant impact on this field in the coming years. Some of these emerging technologies include:

• 3D ICs: 3D integrated circuits are a new type of integrated circuit that stack multiple layers of transistors and other components on top of each other. This technology offers many benefits, including increased performance, reduced power consumption, and improved reliability.
• CMOS Technology: CMOS (Complementary Metal-Oxide-Semiconductor) technology is the dominant technology for fabricating VLSI circuits, and researchers are continuously working on improving this technology. They are developing new techniques for improving the performance, reducing the power consumption, and increasing the reliability of CMOS-based VLSI circuits.
• Advanced Semiconductor Materials: Researchers are investigating new materials that can be used to fabricate VLSI circuits, with the aim of producing integrated circuits that are faster, more reliable, and consume less power.
• Research areas in VLSI Design and Technology:
• Circuit Design and Optimization: With the increasing demand for high-performance and low-power electronic devices, there is a growing interest in developing new circuit design techniques that can optimize the performance of VLSI circuits. Researchers are exploring ways to improve the efficiency of power consumption, reduce the heat generated by the circuits, and enhance the overall performance of the devices.
• Low-Power VLSI Design: Low-power VLSI design is a critical area of research in VLSI design and technology, as it enables the development of high-performance and energy-efficient electronic devices. Researchers are exploring various low-power design techniques, including dynamic voltage and frequency scaling, power gating, and multi-threshold CMOS (Complementary Metal-Oxide Semiconductor) technology, to reduce the power consumption of VLSI circuits.
• Reliability and Testability: Reliability and testability are crucial factors that impact the performance of VLSI circuits. Researchers are exploring various techniques, including built-in self-test (BIST) and built-in self-repair (BISR), to improve the reliability and testability of VLSI circuits, thereby ensuring the high quality of the devices.
• 3D Integration and Packaging: 3D integration and packaging is an emerging area of research in VLSI design and technology, as it enables the integration of multiple layers of devices on a single chip, thereby increasing the performance and functionality of the devices. Researchers are exploring various 3D integration and packaging techniques, including through-silicon vias (TSVs) and interposers, to achieve high-density and high-performance integration.
• Advancements in Artificial Intelligence: With the increasing use of artificial intelligence (AI) in various applications, there is a growing interest in developing VLSI circuits that can support AI algorithms. Researchers are exploring ways to integrate AI hardware accelerators on VLSI chips, thereby enabling the development of high-performance and low-power AI devices.

Future Trends in VLSI Design and Technology:

Emerging Nanotechnologies: Nanotechnology is an emerging area of research in VLSI design and technology, as it enables the development of nanoscale electronic devices that can provide improved performance and functionality. Researchers are exploring various nanotechnologies, including carbon nanotubes and graphene, to develop high-performance and low-power VLSI circuits.

Development of Internet of Things (IoT) Devices: The rapid development of the Internet of Things (IoT) is driving the demand for VLSI devices that can support the connectivity and communication requirements of IoT devices. Researchers are exploring ways to integrate VLSI circuits with IoT technologies, such as wireless communication protocols and sensor interfaces, to enable the development of high-performance and low-power IoT devices.

References:

A. B. Chapple, “VLSI design: system-on-chip design and verification,” Springer, 2004.

K. Roy, “VLSI Design Methodologies for Digital Signal Processing Circuits,” Springer, 2009.

R. J. Baker, “VLSI design techniques for analog and digital circuits,” McGraw-Hill, 2000.

B. Razavi, “Design of analog CMOS integrated circuits,” McGraw-Hill, 2001.

W. Wolf, “Modern VLSI design: system-on-chip design,” Pearson Education, 2006.

J. Rose, “VLSI design for manufacturing: yield enhancement,” Springer, 2002.

H. J. W. Spiess, “VLSI design for high-speed frequency synthesis,” Springer, 2002.

K. Eshraghian, D. Eshraghian, and B. F. Spencer Jr., “Principles of CMOS VLSI design: a systems perspective,” Addison-Wesley, 1990.

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