vlsi research topics list

VLSI Research Topics Ideas [MS PhD]

List of Research Topics and Ideas of VLSI for MS and Ph.D. Thesis.

High-throughput VLSI architecture for soft-decision decoding with ORBGRAND
Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design
VLSI mask optimization: From shallow to deep learning
Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal
A Novel High-Performance Hybrid Full Adder for VLSI Circuits
PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique
Testing single via related defectsin digital VLSI designs
An Improved Impulse Noise Removal VLSI Architecture Using DTBDM Method
VLSI Implementation of Multi-channel ECG Lossless Compression System
A Scalable VLSI Architecture for Illumination-Invariant Heterogeneous Face Recognition
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support
Compact 3D Thermal Model for VLSI and ULSI Interconnect Network Reliability Verification
Simultaneous Parametric and Functional Testing of Digital VLSI During Radiation Experiments
A New 4-2 Compressor for VLSI Circuits and Systems
An ultra-low-power CNFET-based improved Schmitt trigger design for VLSI sensor applications
Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits
Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting
A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box
High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND
Methods for Ensuring Full Traceability of the Production Testing Results of the Digital VLSI
Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology
Fast Auto-Correction algorithm for Digital VLSI Circuits
Review of VLSI Architecture of Cryptography Algorithm for IOT Security
The VLSI Realization of Sign-Magnitude Decimal Multiplication Efficiency
Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications
VLSI design of a fast one-stage independent component extracting system based on ICA-R algorithm
Fully Reused VLSI Architectu Encoding for DSRC Applica
VLSI Architecture for DWT using 5/3 Wavelet Coefficient using Vedic Math’s
Design and vlsi implementation of a decimation filter for hearing aid applications
Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design
A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system
Study and Analysis of Digital Counters for VLSI Applications
Synthesis of VLSI Structural Cell Partitioning Using Genetic Algorithm
VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate
Features of Designing Digital Processing Systems for Radiolocation Systems Based on Microprocessor VLSI Sets
Multiple-Criteria Decision Analysis Using VLSI Global Routing
Performance Evaluation of VLSI Implemented WSN Algorithms
Soft Error Rate Estimation of VLSI Circuits
Wave pipelined VLSI architecture for a Viterbi decoder using self reset logic with 0.65 nm technology
Efficient Band Offset Calculation Method for HEVC and Its VLSI Implementation
2021 IEEE 39th VLSI Test Symposium (VTS)
A spike based learning neuron in analog VLSI
Computing Orientation of an Image by Projection Method and its VLSI Implementation
A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
The First Ge Nanosheets GAAFET CMOS Inverters Fabricated by 2D Ge/Si Multilayer Epitaxy, Ge/Si Selective Etching
Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure
Back-Gate Network Extraction Free from Dynamic Self-Heating in FD SOI
Improvement of Nanotwinned Copper Thermal Stability for High Temperature Heterogeneous Integration
DFT Models of Ferroelectric Hafnium-Zirconium Oxide Stacks With and Without Dielectric Interlayers
Selective Area Epitaxy of Axial Wurtzite-InAs Nanowire on InGaAs NW by MOCVD
Calculation of Field Dependent Mobility in MoS2 and WS2 with Multi-Valley Monte Carlo Method
Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density
Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering
On-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems
Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage
Quantum Tunneling PUF: A Chip Fingerprint for Hardware Security
Ferroelectric and Antiferroelectric Hf/Zr oxide films: past, present and future
An Approach to Diminish the Leakage Power in Complementary MOS VLSI Circuits
Benchmarking the Performance of Heterogeneous Stacked RRAM with CFETSRAM and MRAM for Deep Neural Network Application Amidst Variation and Noise
Multi-bit cryogenic flash memory on Si/SiGe and Ge/GeSi heterostructures
Tensor-Centric Processor Architecture for Applications in Advanced Driver Assistance Systems
Evaluation de la complexit d’implantation en VLSI par la synth se architecturale: une exp rience en filtrage adaptatif
A precise debugging method and defect diagnosis with mass big-data analysis in the designed high-dense array for rapid yield improvement in a logic platform
Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC Platform
Bandgap-Engineered Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Devices
Reconfigurable Database Processor for Query Acceleration on FPGA
Holistic and In-Context Design Flow for 2.5 D Chiplet-Package Interaction Co-Optimization
ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design
Quantum dot celluar automata-based encoder and priority encoder circuits: Low latency and area efficient design
Shutdown mode implementation for Boost and Inverting Buck-Boost converter
AN ELEGANCE OF A NOVEL DIGITAL FILTER USING MAJORITY LOGIC FOR SNR IMPROVEMENT IN SIGNAL PROCESSING
Recent Progress on Flexible Capacitive Pressure Sensors: From Design and Materials to Applications
Prototypage d’algorithmes adaptatifs par un outil de synthèse d’architectures VLSI.
ALGORITMOS PARA PROBLEMAS DE STEINER COM APLICAÇÕES EM PROJETO DE CIRCUITOS VLSI
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
Prospective incorporation of booster in carbon interconnects for high-speed integrated circuits
Laser beam testing of finished integrated circuits
A survey of in-spin transfer torque mram computing
Oxytocin modulates neural processing of mitral/tufted cells in the olfactory bulb
Power Efficient Bit Lines: A Succinct Study
Introduction: Soft Error Modeling
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation
Adiabatic Logic-Based Area-and Energy-Efficient Full Adder Design
Improved Noise Margin and Reduced Power Consumption in Subthreshold Adiabatic Logic Using Dual Rail Power Supply
IMPROVING SIZE-BOUNDS FOR SUBCASES OF SQUARE-SHAPED SWITCHBOX ROUTING
Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology
Qualitative and quantitative analysis of parallel-prefix adders
4-Bit Ripple Carry Adder Using Area-Efficient Full Adder in CMOS Technology
Systolic-Architecture-Based Matrix Multiplications and Its Realization for Multi-Sensor Bias Estimation Algorithms
BiPart: a parallel and deterministic hypergraph partitioner
Dealing with Aging and Yield in Scaled Technologies
Ultraefficient imprecise multipliers based on innovative 4: 2 approximate compressors
A Low Power Approach for Designing 12-Bit Current Steering DAC
Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization
Gain-Cell Embedded DRAM Under Cryogenic Operation–A First Study
Communication and performance evaluation of 3-ary n-cubes onto network-on-chips
A New Function Mapping Approach in Defective Nanocrossbar Array Using Unique Number Sequence
Design, Simulation and Comparative Analysis of Performance Parameters of a 4-bit CMOS based Full Adder Circuit using Microwind and DSch at Various …
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems
Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit
Carver Mead:” It’s All About Thinking,” A Personal Account Leading up to the First Microwave Transistor
Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder
Advanced Silicon & Semiconducting Silicon-Alloy Based Materials & Devices
A Novel Modeling-Attack Resilient Arbiter-PUF Design
Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links
Parallel algorithms
Transistor self-heating: The rising challenge for semiconductor testing
Adaptive Forward Body Bias Voltage Generator
PVT Aware Analysis of ISCAS C17 Benchmark Circuit
Hard-to-Detect Fault Analysis in FinFET SRAMs
Design and comparative analysis of on-chip sigma delta ADC for signal processing applications
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs
Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems
Impact of Spacers in Raised Source/Drain 14 nm Technology Node InGaAs-nFinFET on Short Channel Effects
High Speed Energy Efficient Multiplier Using 20nm FinFET Technology
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits
Design and Analysis of 10T SRAM Cell with Stability Characterizations
Evaluation of Real-Time Embedded Systems in HILS and Delay Issues
Implementation and Analysis of Low Power Consumption Full Swing GDI Full Adders
A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory
[HTML][HTML] X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution
A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n-and p-type Flip-Flops
Variability Analysis of On-Chip Interconnect System Using Prospective Neural Network
Low Power NAND Gate–based Half and Full Adder/Subtractor Using CMOS Technique
Synchronization of mutual coupled fractional order one-sided lipschitz systems
Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register
High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone
Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator
Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V
Machine-learning-based self-tunable design of approximate computing
A novel current-controlled memristor-based chaotic circuit
Performance Analysis of MoS2FET for Electronic and Spintronic Application
Asynchronous Four-Phase and Two-Phase Circuits: Testing and Design for Testability
Controlling GIDL Using Core–Shell Technique in Conventional Nano-Wire
New FDNR and FDNC Simulation Configurations Using Inverted VDDIBAs
Optimal Mappings of the Spectrum of BPSK/QPSK Sequences to Finite Polynomial Fields and Rings
Impact of Multi-Metal Gate Stacks on the Performance of ß-Ga2O3 MOS Structure
On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM
Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Operating at Room Temperature
HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter Banks
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation
Design of a new BUS for low power reversible computation
Controlling Mode Transition Noise Occurred at Ground Rail in Data Preserving MTCMOS Shift Register
Diversity Schemes in Multi-hop Visible Light Communications for 6G Networks
Fabrication of Micro-Compliant Mechanisms Using Micro-Stereolithography
A 27S/32S DC-balanced line coding scheme for PAM-4 signaling
Game Theory-based Parameter-Tuning for Path Planning of UAVs
A Low Latency Stochastic Square Root Circuit
New Resistorless FDNR Simulation Configuration Employing CDDITAs
An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0 V
Improved Store-Carry-Forward Scheme for Information Dissemination in Unfavorable Vehicular Distribution
Effect of surface modification treatment on top-pinned MTJ with perpendicular easy axis
Design and Implementation of an Efficient Mixed Parallel-Pipeline SAD Architecture for HEVC Motion Estimation
Negative Voltage Generator and Current DAC Based Regulator For Flash Memory
A non-autonomous chaotic system with no equilibrium
SIXOR: Single-Cycle In-Memristor XOR
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
Towards energy-efficient STT-MRAM design with multi-modes reconfiguration
HT-IWT-DCT-Based Hybrid Technique of Robust Image Watermarking
GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits
Performance Evaluation of Sub 5 nm GAA NWMBCFET using Silicon Carbide Source/Drain Material
A novel ultra-low power 7T full adder design using mixed logic
Reversible Fade Gate as Decoder, Encoder and Full Adder
A novel parallel prefix adder for optimized Radix-2 FFT processor
Smart Soldier Health Monitoring System Incorporating Embedded Electronics
Theoretical Analysis of Defected Ground Multiband Rectangular Shape Microstrip Patch Antenna
Design of Efficient Ternary Subtractor
Novel CDDITA-Based-Grounded Inductance Simulation Circuits
Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation
Ferroelectric HfO2 Memory Transistors with High-? Interfacial Layer and Write Endurance Exceeding 1010 Cycles
Design and Analysis of Low-Power SRAM
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic
Selective Flip-Flop Optimization for Circuit Reliability
Effect of Developer Temperature on Photoresist Contrast in Grayscale Lithography
Power Series Representation Op logical Functions and its Applications to Error Detection and Error Correction Codes.(Dept. E)
Creating Fastest Self timing Reference Path for High Speed Memory Designs
Blockchain-enabled traceable, transparent transportation system for blood bank
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System
Enhancement of ovonic threshold switching characteristics using nanometer-scale virtual electrode formed within ultrathin hafnium dioxide interlayer
Neural networks integrated circuit with switchable gait pattern for insect-type microrobot
Analog and Radio-Frequency Performance of Hetero-Gate-Dielectric FD SOI MOSFET in Re-S/D Technology
Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications
Field-free and sub-ns magnetization switching of magnetic tunnel junctions by combining spin-transfer torque and spin–orbit torque
Fundamentals of microelectronics
Comparative Analysis of Channel Estimation Techniques in Vehicular Communication
Statistical analysis of vehicle detection in the ITS application for monitoring the traffic and road accident using internet of things
3-D CMOS chip stacking for security ICs featuring backside buried metal power delivery networks with distributed capacitance
Sensor Localization in WSNs Using Rotating Directional-Antenna at the Base Station
A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications
FPGA implementation of fast digital FIR and IIR filters
Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets Using Double Ge0.95Sn0.05 Caps by Highly Selective Isotropic Dry Etch
A 3–7 GHz CMOS Power Amplifier Design for Ultra-Wide-Band Applications
Fault-tolerant hamiltonian cycles and paths embedding into locally exchanged twisted cubes
Error-Controlling Technique in Wireless Communication
Human Action Recognition Using a New Hybrid Descriptor
Minimization of Peak-to-Average Power Ratio in DHT Precoded OFDM System by A-Law Companding
Machine Learning Oriented Dynamic Cost Factors-Based Routing in Communication Networks
Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning
Physical synthesis for advanced neural network processors
A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
On the Best-Partition Communication Complexity
IMPLEMENTATION OF DIVISION AND SQUARE ROOT: MODELING AND EVALUATIONS
Structural and Optical Analysis of Bulk-Hetero Interface Between MoS2: Pentacene
Realization of a Low Profile, Wideband Omni-directional Antenna for Ku-band Airborne Applications
Ultracompact channel add-drop filter based on single multimode nanobeam photonic crystal cavity
Structural and Optical Characterization of EZO Thin Film for Application in Optical Waveguide
Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm
A Survey of Semantic Segmentation on Biomedical Images Using Deep Learning
PAPR Reduction in OFDM for VLC System
A Survey on Proactive and Reactive Channel Switching Techniques in Cognitive Radios
FPGA-based Hardware Acceleration for SVM Machine Learning Algorithm
Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy
A Multichannel Link-Layer Cooperation Protocol (MLCP) for Cognitive Radio Ad Hoc Network
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction
Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling
A PVT aware differential delay circuit and its performance variation due to power supply noise
A Survey on Methodologies and Database Used for Facial Emotion Recognition
A Survey Study of Diseases Diagnosed Through Imaging Methodology Using Ultrasonography
Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept
Automated Simulator for the Validation of Bio-Impedance Devices
The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems
An Optimal Design of 16 Bit ALU
Analysis of Power Adaptation Techniques Over Beaulieu-Xie Fading Model
Design and Analysis of Wearable Step-Shaped Sierpinski Fractal Antenna for WBAN Applications
ASSURE: RTL Locking Against an Untrusted Foundry
Design of Dynamic Induction Charging Vehicle for Glimpse of Future: Cutting Down the Need for High-Capacity Batteries and Charging Stations
Performance Analysis of Speck Cipher Using Different Adder Architectures
A Comparative Analysis of Statistical Model and Spectral Subtractive Speech Enhancement Algorithms
Dimensionality Reduction Using Principal Component Analysis for Lecture Attendance Management System
Design and implementation of current mode circuit for digital modulation
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator
A Compact IPD Based on-Chip Bandpass Filter for 5G Radio Applications
An automated parallel simulation flow for cyber-physical system design
Conformal Omni Directional Antenna for GPS Applications
Recognition of Natural and Computer-Generated Images Using Convolutional Neural Network
SPIDER-based out-of-order execution scheme for Ht-MPSOC
Fast Encoding Using X-Search Pattern and Coded Block Flag Fast Method
Design and Simulation of a Dual-Band Radiometer for Humidity and Temperature Profiling
Voice Controlled IoT Based Grass Cutter Powered by Solar Energy
Periodic Octagon Split Ring Slot Defected Ground Structure for MIMO Microstrip Antenna
COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing
Design of Electronic Instrumentation for Isotope Processing
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution
Design and analysis of improved high-speed adaptive filter architectures for ECG signal denoising
Compact and efficient structure of 8-bit S-box for lightweight cryptography
Virtually Doped Silicon-on-Insulator Junctionless Transistor for Reduced OFF-State Leakage Current
Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks
[HTML][HTML] Design and simulation of high-performance 2: 1 multiplexer based on side-contacted FED
Special Session–Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits
Enhancement of magnetic coupling and magnetic anisotropy in MTJs with multiple CoFeB/MgO interfaces for high thermal stability
Nonlinear Circuits and Systems with Memristors: Nonlinear Dynamics and Analogue Computing via the Flux-Charge Analysis Method
The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising
Information Theory-Based Defense Mechanism Against DDOS Attacks for WSAN
TxSim: Modeling training of deep neural networks on resistive crossbar systems
Automated Observability Analysis for Mixed-Signal Circuits
Silicon-on-nothing electrostatically doped junctionless tunnel field effect transistor (son-ed-jltfet): A short channel effect resilient design
Fault Detection and Classification in Microgrid Using Wavelet Transform and Artificial Neural Network
[HTML][HTML] Development of neural networks chip generating driving waveform for electrostatic motor
Computer Laboratory
Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing
Recent Development in Analytical Model for Graphene Field Effect Transistors for RF Circuit Applications
Phenomenological CNN model of a somatosensory effects
Reusability and Scalability of an SoC Testbench in Mixed-Signal Verification—The Inevitable Necessity
Power-and area-optimized high-level synthesis implementation of a digital down converter for software-defined radio applications
3–21 GHz broadband and high linearity distributed low noise amplifier
64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure
Resynthesize Technique for Soft Error-Tolerant Design of Combinational Circuits
FPGA implementations for data encryption and decryption via concurrent and parallel computation: A review
Vertically integrated computing labs using open-source hardware generators and cloud-hosted FPGAs
Fast shared-memory streaming multilevel graph partitioning
Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology
Hybrid Forecasting Model Based on Nonlinear Auto-Regressive Exogenous Network, Fourier Transform, Self-organizing Map and Pattern Recognition Model for Hour …
Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency
Design of Low Power Barrel Shifter Architecture by Using Proposed MUX Based CORDIC in CMOS Logic
Adaptive filtering algorithms in acoustic echo cancellation: a case study in architecure complexity evaluation
Performance improvement of elliptic curve cryptography system using low power, high speed 16× 16 Vedic multiplier based on reversible logic
Density Gradient Study on Junctionless Stack Nano-Sheet with Stack Gate Oxide for Low Power Application
All-digital built-in self-test scheme for charge-pump phase-locked loops
FPGA Hardware Acceleration of Soft Error Rate Estimation of Digital Circuits
Power-aware hold optimization for ASIC physical synthesis
Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits
New LMI Criterion to the Robust Stability of Discrete-Time Systems with Time-Varying Delays and Generalized Overflow Nonlinearities
A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks
FPGA Design of SAR Type ADC Based Analog Input Module for Industrial Applications
Secure energy efficient network priority routing protocol for effective data collection and key management in dynamic WSNs
A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
Monolithic 3D stacked multiply-accumulate units
Guidance-based improved depth upsampling with better initial estimate
Circuit and system-level aspects of phase change memory
An Active, Low-Power, 10Gbps, Current-based Transimpedance Amplifier in a Broadband Optical Receiver Front-End
Conception de deux points mémoire statiques CMOS durcis contre l’effet des aléas logiques provoqués par l’environnement radiatif spatial
Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits. Electronics 2021, 10 …
A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
Design and Fabrication of a Polymer Microring Resonator: Polymer Microring Resonator
Design for Testability of Low Dropout Regulators
Magnonic band structure in CoFeB/Ta/NiFe meander-shaped magnetic bilayers
Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic
Higher-order Network Analysis Takes Off, Fueled by Classical Ideas and New Data
High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic
Enhancement-Mode Atomic-Layer-Deposited In2O3 Transistors With Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing …
Design of High-Speed Binary Counter Architecture for Low-Power Applications
A Systematic Review on an Embedded Web Server Architecture
Build-in compact and efficient temperature sensor array on field programmable gate array
SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level
Low power, high-performance reversible logic enabled CNTFET SRAM cell with improved stability
Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol
A Reconfigurable Architecture to Implement Linear Transforms of Image Processing Applications
Etude du bruit électrique en 1/f et des fluctuations RTS aux basses fréquences dans le transistor MOS submicronique
sonal communication, June 16, 1994.
In-memory realization of SHA-2 using ReVAMP architecture
Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
Design and validation of an artificial neural network based on analog circuits
Insight into threshold voltage and drain induced barrier lowering in negative capacitance field effect transistor
The past and future of multi-gate field-effect transistors: Process challenges and reliability issues
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS……………….. K. Shiba …
[HTML][HTML] A Survey on Application Specific Processor Architectures for Digital Hearing Aids
A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era
Multilevel Hypergraph Partitioning with Vertex Weights Revisited
[HTML][HTML] The involution tool for accurate digital timing and power analysis
Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency. Electronics 2021, 10, 71
Memristor based high speed and low power consumption memory design using deep search method
Comparative Analysis of Adder for Various CMOS Technologies
Design of Parallel Sorting System Using Discrete-Time Neural Circuit Model
Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits
Process Variation-Aware Soft Error Rate Estimation Method for Integrated Circuits
Global placement with deep learning-enabled explicit routability optimization
Microcomputer Application in Motion Control
Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip
Capacitance-to-Digital Converter for Operation under Uncertain Harvested Voltage down to 0.3 V with No Trimming, Reference and Voltage Regulation
Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications
A Theoretical Study of Design Rewiring Using ATPG
FPGA Implementation of Bio-inspired Computing Based Deep Learning Model
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
Employing the Empirical Mode Decomposition to Denoise the Random Telegraph Noise
Dependence of metal gate work function variation for various ferroelectric thickness on electrical parameters in NC-FinFET
[HTML][HTML] A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs
Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components
FPGA Implementation of Radix-4-Based Two-Dimensional FFT with and Without Pipelining Using Efficient Data Reordering Scheme
TRENDS IN DISTRIBUTED OBJECT COM-PUTING
Designing a New 4: 2 compressor using an efficient multi-layer full-adder based on nanoscale quantum-Dot cellular automata
Introduction to Dual Mode Logic (DML)
3-D IC: An Overview of Technologies, Design Methodology, and Test Strategies
A Novel Plaintext-Related Color Image Encryption Scheme Based on Cellular Neural Network and Chen’s Chaotic System
Spatial Coverage of FM Radio Signal Variation Measurement and Comparison of two Major Radio Stations within Akwa Ibom State
Fabrication and selective wet etching of Si0. 2Ge0. 8/Ge multilayer for Si0. 2Ge0. 8 channel gate-all-around MOSFETs
High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs
Dynamic workload allocation for edge computing
Non-volatile memory behavior of interfacial InOx layer in InAs nano-wire field-effect transistor for neuromorphic application
A Case Study on FPGA Implementation of Parts Counting Orientation Recognition Method for Industrial Vision System
A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth
A low-power dynamic ternary full adder using carbon nanotube field-effect transistors
Design and analysis of (5, 10) regular LDPC encoder using MRP technique
Low-Voltage DML
Efficient Ternary Compressor Design Using Capacitive Threshold Logic in CNTFET Technology
Realization of 8 x 4 Barrel shifter with 4-bit binary to Gray converter using FinFET for Low Power Digital Applications
Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
High-speed programmable photonic circuits in a cryogenically compatible, visible-NIR 200 mm CMOS architecture
S ntese de Alto N vel de Protocolos para a Abordagem IP sobre ATM
A Systematic Review of Approximate Adders: Accuracy and Performance Analysis
Evaluation of low power consumption network on chip routing architecture
Tiny robots and sensors need tiny batteries—here’s how to do it
Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
Gradual magnetization switching via domain nucleation driven by spin–orbit torque
TEM studies during development of a 4-megabit DRAM
Circuit Design Using Genetic Programming: An Illustrative Study
Machine Learning for Electronic Design Automation: A Survey
Design optimization of sub-5 nm node nanosheet field effect transistors to minimize self-heating effects
Suppression of ambipolar behavior and simultaneous improvement in RF performance of gate-overlap tunnel field effect transistor (GOTFET) devices
Analysis on High-Performance Full Adders
Features of Organizing the Process of Designing Radar Microcircuits
Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays
On the role of system software in energy management of neuromorphic computing
Introduction to nanowires: types, proprieties, and application of nanowires
Unveiling the impact of the bias dependent charge neutrality point on graphene based multi transistor applications
True Random Number Generation using Latency Variations of Commercial MRAM Chips
Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures
Impact of the SiO2 interface layer on the crystallographic texture of ferroelectric hafnium oxide
Voltage-gate assisted spin-orbit torque magnetic random access memory for high-density and low-power embedded application
1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing
Shift Left Trends for Design Convergence in SOC: An EDA Perspective
Domain wall mobility engineering by a perpendicular magnetic field in microwires with a gradient of perpendicular anisotropy
Characterization of QUBO reformulations for the maximum -colorable subgraph problem
State of charge estimation of lithium batteries in electric vehicles using IndRNN
Design of AES-Based Encryption Chip for IoT Security
A 15-bit, 5 MSPS SAR ADC with on-chip digital calibration
Optimization of Low Power LNA Using PSO for UWB Application
Amorphous InGaZnO Thin-Film Transistors With Sub-10-nm Channel Thickness and Ultrascaled Channel Length
Digital Implementation of Sigmoid Function in Artificial Neural Network Using VHDL
Performance Analysis for Tri-Gate Junction-Less FET by Employing Trioxide and Rectangular Core Shell (RCS) Architecture
Design of dopingless GaN nanowire FET with Low ‘Q’for high switching and RF applications
Circuit Design for Non-volatile Magnetic Memory
Post-Moore Memory Technology: Sneak Path Current (SPC) Phenomena on RRAM Crossbar Array and Solutions
An Energy-Efficient UWB Transmitter with Wireless Injection Locking for RF Energy-Harvesting Sensors
A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations
Approximate Multipliers Using Bio-Inspired Algorithm
Fault-Tolerant Implementation of Quantum Arithmetic and Logical Unit (QALU) Using Clifford+T-Group
WADE: A Web-based Automated electronic Design Environment
Hybrid memristor-CMOS implementation of logic gates design using LTSpice.
Towards Scalable Spectral Embedding and Data Visualization via Spectral Coarsening
Half-Select Disturb-Free 10T Tunnel FET SRAM Cell with Improved Noise Margin and Low Power Consumption
Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories
A 4-GS/s 10-ENOB 75-mW ringamp ADC in 16-nm CMOS with background monitoring of distortion
Realization with fabrication of double-gate MOSFET based buck regulator
Two-dimensional transistors with reconfigurable polarities for secure circuits
A NEW DESIGN OF TANGENT HYPERBOLIC FUNCTION GENERATOR WITH APPLICATION TO THE NEURAL NETWORK IMPLEMENTATIONS
A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores
Electromigration in solder joints: A cross-sectioned model system for real-time observation
Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications
M3DSSD: Monocular 3D single stage object detector
A ring oscillator with very low phase noise and wide frequency range using carbon nanotube technology for PLL applications
Towards Next Generation Robust Cryptosystems
Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques
Layout dependence of total-ionizing-dose response in 65-nm bulk Si pMOSFET
Soft-error resilient read decoupled SRAM with multi-node upset recovery for space applications
On-Fly-TOD: an efficient mechanism for crosstalk fault reduction in WNoC
Experimental Examination of Component-Differentially-Challenged XOR PUF Circuits
Implementation of Neuro-Memristive Synapse for Long-and Short-Term Bio-Synaptic Plasticity
BiFeO3 clad modified fiber optic gas sensor for room temperature applications
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs
Macrolide Biosensor Optimization through Cellular Substrate Sequestration
A design towards an energy-efficient and lightweight data security model in Fog Networks
Security of Neural Networks from Hardware Perspective: A Survey and Beyond
An Empirical Study of the Reliability of High-Level Synthesis Tools
Design of low-power coupled chopper instrumentation amplifier using pin pong ripple reduction for biomedical applications
Low Powered Self-Testable ALU
Nanopower multiple-input DTMOS OTA and its applications to high-order filters for biomedical systems
EM Lifetime Constrained Optimization for Multi-Segment Power Grid Networks
Approximate Array Multipliers
Linear k-arboricity of Caylay graphs on Abelian groups with given degree
ObfusX: routing obfuscation with explanatory analysis of a machine learning attack
FPGA-based architecture for bi-cubic interpolation: the best trade-off between precision and hardware resource consumption
Hardware Verification: Theory and Practice
Decomposition Methods of FSM Implementation
Word Length Selection Method for HIL power converter models
Review on performance analysis of P3HT: PCBM-based bulk heterojunction organic solar cells
Silico-Algorithmes et Arithm etique des Ordinateurs
Post-Moore Memory Technology: Sneak Path Current (SPC) Phenomena on RRAM Crossbar Array and Solutions. Micromachines 2021, 12, 50
On the Design of a Fault-Tolerant Scalable Three Dimensional NoC-Based Digital Neuromorphic System With On-Chip Learning
Electric Propulsion Methods for Small Satellites: A Review
Multi-Ferroic Properties on BiFeO3/BaTiO3 Multi-Layer Thin-Film Structures with the Strong Magneto-Electric Effect for the Application of Magneto-Electric Devices
A Systematic Review on Various Types of Full Adders
Superconducting neural networks with disordered Josephson junction array synaptic networks and leaky integrate-and-fire loop neurons
Benchmarking Machine Learning: How Fast Can Your Algorithms Go?
Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process
Multilevel Acyclic Hypergraph Partitioning*
Robust circuit implementation of 4-bit 4-tube CNFET based ALU at 16-nm technology node
Process validation test of CNTFET using Stanford model
Energy-aware routing considering load balancing for SDN: a minimum graph-based Ant Colony Optimization
Traffic sign detection optimization using color and shape segmentation as pre-processing system
Neuromorphic vision sensors: Principle, progress and perspectives
Binary Decision Diagrams
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Dual Mode Logic in FD-SOI Technology
Spin–orbit torque and Dzyaloshinskii–Moriya interaction in perpendicularly magnetized heterostructures with iridium
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Website Development for Trading Between Farmers and Government
Modeling and experimental analysis of an internally-cooled vapor chamber
Logic Synthesis of Sequential Logic Circuits for Adiabatic Quantum-Flux-Parametron Logic
Further stability analysis of neutral-type Cohen-Grossberg neural networks with multiple delays
Perspective on ferroelectric, hafnium oxide based transistors for digital beyond von-Neumann computing
Verilog Implementation of Biometric-Based Transmission of Fused Images Using Data Encryption Standards Algorithm
Learned smartphone isp on mobile npus with deep learning, mobile ai 2021 challenge: Report
Domain wall-magnetic tunnel junction spin–orbit torque devices and circuits for in-memory computing
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node
Enhancing Security and Trust of IoT Devices–Internet of Secured Things (IoST)
Dual Metal Double Gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with Hetero Dielectric: DC & Analog Performance Projections
DML Energy-Delay Tradeoffs and Optimization
Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application
RECON: Resource-efficient CORDIC-based neuron architecture
A compensation textures dehazing method for water alike area
An Efficient Hardware Architecture for Deblocking Filter in HEVC
Toward novel designs of reversible ternary 6: 2 Compressor using efficient reversible ternary full-adders
3D-aCortex: An ultra-compact energy-efficient neurocomputing platform based on commercial 3D-NAND flash memories
Study and Implementation of Ladder Logic Conversion to VHDL for Field Programmable Gate Array (FPGA)-Based Programmable Logic Controllers (PLC)
Enhanced Lubrication Ability of Polyalphaolefin and Polypropylene Glycol by COOH-Functionalized Multiwalled Carbon Nanotubes as an Additive
A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes
[HTML][HTML] Mathematical optimization approach for facility layout on several rows
Mobility enhancement techniques for Ge and GeSn MOSFETs
Towards the development of backing layer for piezoelectric micromachined ultrasound transducers
EN SYNTHESE D’ARCHITECTURE
Implementation of Autoencoders with Systolic Arrays through OpenCL
Ultra-high-performance magnetic nonvolatile level converter flip-flop with spin-hall assistance for dual-supply systems with power gating architecture
Adaptive Deconvolution-based stereo matching Net for Local Stereo Matching
Investigation of thick GaAs: Cr pixel sensors for X-ray imaging applications
Damage in silicon after reactive ion etching
Unraveling the optical contrast in Sb2Te and AgInSbTe phase-change materials
Emerging technologies and the security of western Europe
An overview of biological applications and fundamentals of new inlet and vacuum ionization technologies
Realization of a self-powered ZnSnO MSM UV photodetector that uses surface state controlled photovoltaic effect
Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles
Lowering the Schottky Barrier Height by Titanium Contact for High-Drain Current in Mono-layer MoS 2 Transistor
Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application
On the crossing numbers of join products of W_ {4}+ P_ {n} and W_ {4}+ C_ {n}
A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets
Visibilidade em Poligonos utilizando algoritmos paralelos
Um Protocolo SR ARQ Ponto-a-Multiponto com Reconhecimento Acumulativo para Comunica cões a Altas Velocidades
Deep-Learning Assisted Compact Modeling of Nanoscale Transistor
Proposed pipeline clocking scheme for microarchitecture data propagation delay minimization
Ultralow-loss silicon nitride waveguides for nonlinear optics
[HTML][HTML] Benchmarking monolayer MoS 2 and WS 2 field-effect transistors
Phase Change Random Access Memory for Neuro-Inspired Computing
Security of Emerging Memory Chips
Study on Power Minimization techniques in SAR ADC Devices by Using Comparators Circuits
Built-In Self-Test (BIST) Methods for MEMS: A Review
AXON: NETWORK VIRTUAL STORAGE DESIGNz
IOT-HARPSECA: A Secure Design and Development System of Roadmap for Devices and Technologies in IOT Space
[HTML][HTML] High performance IIR filter implementation on FPGA
Terrestrial precise positioning system using carrier phase from burst signals and optically distributed time and frequency reference
Generation of Pseudorandom Sequence Using Regula-Falsi Method
A fractional-order CNN hyperchaotic system for image encryption algorithm
Genfloor: Interactive generative space layout system via encoded tree graphs
Our Perspectives
Transformations of Rectangular Dualizable Graphs
High-speed CMOS-compatible III-V on Si membrane photodetectors
Configurable DSI partitioned approximate multiplier
Stacking faults and precipitates in annealed and co-sputtered C49 TiSi2 films
Trading-o Power versus Area through a Parameterizable Model for Virtual Memory Manage
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency
Internet Rescue Robots for Disaster Management [J]
Reliable advanced encryption standard hardware implementation: 32-bit and 64-bit data-paths
A new opportunity for the emerging tellurium semiconductor: resistive switching device implementation
[HTML][HTML] Simulation and experimental verification of modified sinusoidal pulse width modulation technique for torque ripple attenuation in Brushless DC motor drive
Ordered Binary Decision Diagrams, Gaussian Elimination and Graph Theory
Monitor Circuits for Cross-Layer Resiliency
TSV Fault Contactless Testing Method Based on Group Delay
[HTML][HTML] An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation
EBIC diffusion length of dislocated silicon
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A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
Influence of High-Pressure Annealing Conditions on Ferroelectric and Interfacial Properties of Zr-Rich Hf?Zr1??O2Capacitors
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops
Field-programmable gate arrays in a low power vision system
On undirected two-commodity integral flow, disjoint paths and strict terminal connection problems
Scheduling Conditional Nested Loops in a Resource Constrained ASIC Design
Reliability-Aware Multipath Routing of Time-Triggered Traffic in Time-Sensitive Networks
Time-domain computing in memory using spintronics for energy-efficient convolutional neural network
End-to-End Data Architecture Considerations for IoT
Covering problem on fuzzy graphs and its application in disaster management system
A Time-Frequency Measurement and Evaluation Approach for Body Channel Characteristics in Galvanic Coupling Intrabody Communication
Crosstalk minimization in network on chip (NoC) links with dual binary weighted code CODEC
A physical model for bulk gate insulator trap generation during bias-temperature stress in differently processed p-channel FETs
On the capabilities of Cellular Automata-based MapReduce model in Industry 4.0
Rail-to-rail dynamic voltage comparator scalable down to pw-range power and 0.15-v supply
In situ microsectioning and imaging of semiconductor devices using a scanning ion microscope
Estimation Probabiliste des Ressources, pour la synth ese d’Architectures
Improved design debugging architecture using low power serial communication protocols for signal processing applications
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Single Event Transient (SET) Mitigation Circuits With Immune Leaf Nodes
A Period-Aware Routing Method for IEEE 802.1 Qbv TSN Networks
Special session: Reliability analysis for ML/AI hardware
The Japanese fifth generation computing project: curricular applications
Proposal for ultrafast all-optical pseudo random binary sequence generator using microring resonator-based switches
Hardware/Software Codesign for Energy Efficiency and Robustness: From Error-Tolerant Computing to Approximate Computing
TAAL: tampering attack on any key-based logic locked circuits
Hardware Trojan Prevention and Detection by Filling Unused Space Using Shift registers, Gate-chain and Extra Routing.
Quiet 2-Level Adiabatic Logic
Towards a DML Library Characterization and Design with Standard Flow
Sedenionic formulation for the field equations of multifluid plasma
Design and analysis of double-gate junctionless vertical TFET for gas sensing applications
Shared-Memory n-level Hypergraph Partitioning
An Improved Adaptive Genetic Algorithm for Two-Dimensional Rectangular Packing Problem
[HTML][HTML] Neuromorphic model of reflex for realtime human-like compliant control of prosthetic hand
Memory applications from 2D materials
Fast multipole method for 3-D Laplace equation in layered media
Dielectric spectroscopy and electrical conductivity measurements of a series of orthoconic antiferroelectric liquid crystalline esters
The unified modeling language reference manual
Design of a 2–30 GHz Low-Noise Amplifier: A Review
Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics
Early Detection of Prediabetes and T2DM Using Wearable Sensors and Internet-of-Things-Based Monitoring Applications
Road surface detection and differentiation considering surface damages
Deep learning-based feature extraction and optimizing pattern matching for intrusion detection using finite state machine
2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local …
Uniform Crystal Formation and Electrical Variability Reduction in Hafnium-Oxide-Based Ferroelectric Memory by Thermal Engineering
REVIEW ON RUDIMENTS OF DIGITAL IMAGE PROCESSING
Computer simulation of X-ray topographs of curved silicon crystals
The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges
Detecting Signature of Virus Using Metamaterial-Based One-Dimensional Multi-layer Photonic Crystal Structure Under Polarized Incidence
A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier
Block coordinate descent based algorithm for computational complexity reduction in multichannel active noise control system
RRAM-Based Neuromorphic Computing Systems
analysis and Simulation of Schottky tunneling using Schottky barrier FET with 2-D analytical modeling
Investigation of Multiple-valued Logic Technologies for Beyond-binary Era
Structure and substructure connectivity of alternating group graphs
Power and area efficient stochastic artificial neural networks using spin–orbit torque-based true random number generator
Improvised hierarchy of Floating Point Multiplication using 5: 3 Compressor
Research on digital image watermark encryption based on hyperchaos
Calibration of WLI Lateral Indication Error with 2D Micro/Nano Pitch Standard
Implementation of Autoencoders with Systolic Arrays through OpenCL. Electronics 2021, 10, 70
State-of-the-Art TFET Devices
1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology
Resilient and Secure Hardware Devices Using ASL
6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency
Comparative Analysis of Rapid Single Flux Quantum (RSFQ) Circuit Technique Multipliers
BiCoSS: toward large-scale cognition brain with multigranular neuromorphic architecture
Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide.
TAN modelling of HH-shape microstrip interconnect tree
Improving efficiency in neural network accelerator using operands hamming distance optimization
Thickness of the subgroup intersection graph of a finite group [J]
A 189×600 Back-Illuminated Stacked SPAD Direct Time-of-Flight Depth Sensor for Automotive LiDAR Systems
A Fully Integrated 2.7 µW-70.2 dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End,-16.5 dB-SIR, FEC and Cryptographic Checksum
Learning complexity of simulated annealing
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework
High Current Density in Monolayer MoS2 Doped by AlOx
A general semantics for logics of affirmation and negation
Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions
Modelling and Design of 5T, 6T and 7T SRAM Cell Using Deep Submicron CMOS Technology
[HTML][HTML] Coupled VO2 oscillators circuit as analog first layer filter in convolutional neural networks
Design of CMOS 6T and 8T SRAM for Memory Applications
Brain-inspired golden chip free hardware trojan detection
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A 0.8 V multimode vision sensor for motion and saliency detection with ping-pong PWM pixel
Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7 TOPS/W for Tiny AI Edge Devices
Electron beam induced artefact during TEM and Auger analysis of multilayer dielectrics
Binary precision neural network manycore accelerator
Deep learning-driven simultaneous layout decomposition and mask optimization

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Integrated Circuits and VLSI

Specialties

Analog Circuits
Data converters
Digital circuits
Energy harvesting
Hardware DSP implementation
Low power circuits
RF circuits
Sensing systems

ECE Faculty

Ehsan afshari, al-thaddeus avestruz, david blaauw, robert dick, michael flynn, seok-hyeon jeong, hun-seok kim, pinaki mazumder, khalil najafi, mehdi saligane, dennis sylvester, david wentzloff, euisik yoon, zhengya zhang, cse faculty, ronald dreslinski, joseph costello awarded rackham predoc to support research on brain-machine interfaces, augmented reality system for accessible play, igym, goes international, u-michigan a partner in two chips act midwest microelectronics hubs, kyumin kwon’s research on automating analog circuit design earns best paper award at smacd23, six ece faculty will help shape the future of semiconductors as part of the jump 2.0 program, open-source hardware: a growing movement to democratize ic design, best paper for a low-power adc circuit for brain-machine interface applications, mike flynn named fawwaz t. ulaby collegiate professor of electrical and computer engineering, prof. david blaauw inducted into micro hall of fame, chips and science act: implications and opportunities, the ethical implications of tech, and why it matters for engineers, batteryless next-generation cellular devices could empower a more sustainable future, snails carrying the world’s smallest computer help solve mass extinction survivor mystery, research to advance low-power speech recognition highlighted by intel, first digital single-chip millimeter-wave beamformer will exploit 5g capabilities, tracking monarch butterfly migration with the world’s smallest computer, u-m startup skygig aims to take 5g to the next level, trevor odelberg receives ndseg fellowship to help run the world with low power batteryless circuits, matthew belz receives ndseg fellowship to improve the safety of autonomous systems, battery-free sensor startup takes aim at industrial efficiency, “ultra low-power receivers for iot applications” wins outstanding invited paper, best paper award for optimizing wireless power transfer, david blaauw named kensall d. wise collegiate professor of electrical engineering and computer science, upgrading signal interfaces for better wearable devices, hun-seok kim receives career award to facilitate internet of things connectivity, two ‘u’ researchers receive distinguished university innovator award, blaauw, sylvester are 2019 distinguished university innovators, first programmable memristor computer aims to bring ai processing down from the cloud, afshari group receives best invited paper award at the 2019 ieee custom integrated circuits conference, a high-efficiency gaas solar cell to power the internet of tiny things, slam-ming good hardware for drone navigation, u-m startup raises $6 million in venture funding, communicating with the world’s smallest computers, crafting better digital systems with ece phd student jie-fang zhang, michigan chips will be first to test next-generation hardware design tools, a new hybrid chip that can change its own wiring, enabling anyone to design hardware with a new open-source tool, hun-seok kim receives darpa young faculty award to advance research in iot networks, an even smaller world’s smallest ‘computer’, seed-sized u-m computers pumped into oil wells featured at the houston museum of natural science, fred buhler builds better chips for “aweslome” applications, 2017 isca influential paper award for groundbreaking research in power-efficient computing, michigan’s millimeter-scale computers featured at isscc2017, and in ieee spectrum, cubeworks: solving problems with the world’s smallest and lowest-power computers, alum startup wins $25,000 at accelerate michigan competition, injectable computers can broadcast from inside the body, injectable computers, avish kosari selected as barbour scholar for research in low-power devices for the internet of things, googling the physical world, claude gauthier and omniphy: connecting to the ethernet revolution, 3 ece companies make the silicon 60 list – again, david wentzloff receives joel and ruth spira excellence in teaching award, thomas chen earns nsf graduate research fellowship for research in artificial neural networks for computer vision, elnaz ansari earns towner prize for distinguished academic achievement, michigan micro mote (m3) makes history as the world’s smallest computer, prof. michael flynn elected ieee fellow for contributions to analog-digital interfaces, lynn conway receives 2015 ieee/rse james clerk maxwell medal, leaders in ultra low power cicuits and systems presenting at vlsi circuits symposium, thank lynn conway for your cell phone, student spotlight: nathan roberts – enabling the internet of things, psikick startup attracts financing for its internet of things technology, muhammad faisal wins business competition with technology critical to the internet of things, making the internet of things happen, image processing 1,000 times faster is goal of new $5m contract, zhengya zhang receives intel early career award, 2013 design automation conference anniversary awards, bharan giridhar awarded rackham predoctoral fellowship for research in circuit techniques for adaptive, reliable, high-performance computing, david blaauw and dennis sylvester named top authors by isscc, david wentzloff receives career award for research in energy-autonomous systems, nathan roberts earns best paper award for research to assist in remote patient monitoring, developing the wireless component for personalized health devices, ug research spotlight: fred buhler spends his summer improving circuit testing, student teams earn prizes for their analog/digital interface circuit designs in eecs 511, michael mccorquodale named 2012 ubm electronics ace innovator of the year, prof. david blaauw elected fellow of the ieee, laura freyman awarded nsf graduate research fellowship, powering breakthrough technologies, toward computers that fit on a pen tip: new technologies usher in the millimeter-scale computing era, three eecs teams are winners in 2011 dac/isscc student design contest, zhengya zhang receives nsf career award, paving the way for ubiquitous computing, prof. dennis sylvester elected fellow of the ieee, meeting the challenges for low-power system-on-chip (soc) design, zhengya zhang earns best paper award at symposium on vlsi circuits, ambiq micro: taking a startup to the next level, millimeter-scale, energy-harvesting sensor system developed, eecs professors receive research grants from google, prof. david wentzloff awarded young faculty award (yfa) by darpa, sensing sensors: nsf funding news ways to monitor infrastructure for safety, eecs researchers receive best paper award at islped.

Special issue: 26th international symposium on VLSI design and test 2022

Published: 08 September 2023
Volume 116 , pages 1–3, ( 2023 )

Cite this article

Ambika Prasad Shah 1 &
Sudeb Dasgupta 2

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1 Introduction

The increasing versatility, performance, compactness and power efficiency of today’s electronic systems is achieved by pushing technology to its physical limits; systems are increasing in size and complexity, comprising thousands of subsystems made of billions of devices. The devices themselves have become smaller and smaller and have reached the atomic scale.

This Special Issue aimed at continuing the discussion about the research activities and related findings carried out the 26th International Symposium on VLSI Design and Test (VDAT-2022) held in Jammu, India, July 17- 19th 2022 with the theme of “Chips to Startup for sustainable development”. Therefore, this Special Issue focuses on the following areas:

Emerging Devices and Material Technologies.

VLSI Circuit and System Design.

IC Reliability, Security and Quality.

CAD for VLSI, Testing and Verification.

FPGA based Design and Embedded Systems.

2 Topics of the special issue

This special issue comprises 7 articles selected after a rigorous review process of the extended versions of papers presented at VDAT-2022. Accepted articles covers various aspects of microelectronics devices, ADC, in-memory computation, reliability and security in integrated circuits, various architectures and devices, and focusing at different levels of abstraction from device level to system level.

Paper “Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing” by Kavita Monga et al. [ 1 ] address the two major issues with the in-memory computation. For precise operation, the applied input signals must be stable and during the input signal generation is the deviation in the width values due to process, voltage, and temperature variations. Authors have proposed to design a tunable delay line that provides a linear PWM signal corresponding to an input vector which is further utilized to perform local computation in memory.

Paper “Cadmium sulfide deposition suited for photo pattern-based SAW device” by Rahul Sharma et al. [ 2 ] demonstrates a surface acoustic wave (SAW) device based on photopatterned interdigital transducer (IDT) created on a cadmium sulfide layer deposited over a lithium niobate substrate using two methods, viz. chemical bath deposition (CBD) and spin-coating. I–V characteristics are measured for photo pattern-based SAW devices with different electrode separation widths.

Paper “Design of a high precision CMOS programmable gain and data rate delta sigma ADC” by Mohd Asim Saeed et al. [ 3 ] presents a general purpose high precision Delta Sigma (ΔΣ) ADC with a common mode rejection of 100 dB, developed for data acquisition of sensors used in a satellite launch vehicle telemetry system. The ADC is also equipped with on chip offset and gain calibration features to reduce the offset and gain errors.

Paper “Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications” by Arvind Bisht et al. [ 4 ] proposes an optimized Nanosheet Transistor (NSHT) with an inner high-k spacer and an underlap region. A symmetric dual-k spacer structure and an undoped underlap region are incorporated into the baseline device to optimize it for better performance. The analog performance of the optimized NSHT is compared with the performance of the baseline NSHT device across the design space.

Paper “A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issues” by Subrata Das et al. [ 5 ] propose an algorithm for the routing of Graphene nanoribbon based interconnect considering minimization of grid area and improvement of interconnect-reliability as the optimization goals with minimum increase in interconnect resistance and delay.

Paper “BTI resilient TG-based high-performance ring oscillator for PUF design” by Shubhang Srivastava et al. [ 6 ] propose a new energy-efficient and aging resilient inverter and ring oscillator based on an aging resilient inverter design. The proposed inverter is 22.57% less power-consuming and 16% faster than the conventional Aging Resilient inverter while showing nearly identical aging characteristics without significant increment in area overhead. Authors also designed ring oscillator from the proposed inverter shows nearly 1.5% higher frequency than the conventional aging resilient ring oscillator for the same number of inverter stages.

Paper “Efficient hardware implementations of Lopez–Dahab projective co-ordinate based scalar multiplication of ECC” by M. Mohamed Asan Basiri [ 7 ] proposes efficient hardware implementations scalar multiplication of Lopez–Dahab projective co-ordinate based ECC in the platforms of application specific integrated circuit (ASIC) and field programmable gate array logic (FPGA). Due to this dual core implementation in FPGA, the throughput of the proposed scalar multiplication in FPGA is greater than various existing designs.

3 Conclusion

All of the papers selected for this Special Issue represent world-leading current research into robust and novel devices, reliability-aware design and hardware security approaches for computing systems and provide interesting and valuable insights into current and future trends and issues within these areas. We hope you will enjoy reading the papers and find them a source of inspiration for your own work.

Monga, K., Shenoy, M. V., Chaturvedi, N., et al. (2023). Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02169-5 .

Article Google Scholar

Sharma, R., & Nemade, H. B. (2023). Cadmium sulfide deposition suited for photo pattern-based SAW device. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02172-w .

Saeed, M. A., Srivastava, R. K., Sehgal, D., et al. (2023). Design of a high precision CMOS programmable gain and data rate delta sigma ADC. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02165-9 .

Bisht, A., Pundir, Y. P., & Pal, P. K. (2023). Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02171-x .

Das, S., Das, D. K., & Pandit, S. (2023). A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issues. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02170-y .

Srivastava, S., Verma, A., & Shah, A. P. (2023). BTI resilient TG-based high-performance ring oscillator for PUF design. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02180-w .

M. Mohamed Asan, Basiri Efficient hardware implementations of Lopez–Dahab projective co-ordinate based scalar multiplication of ECC. Analog Integrated Circuits and Signal Processing . https://doi.org/10.1007/s10470-023-02179-3

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Acknowledgements

We sincerely thank all the reviewers for helping us in reviewing the papers in time. We also thank all the staff members of Analog Integrated Circuits and Signal Processing journal for their effortless support. Last but not the least we thank the Editor-in-Chief and handling editor for their help and support throughout the entire process.

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Shah, A.P., Dasgupta, S. Special issue: 26th international symposium on VLSI design and test 2022. Analog Integr Circ Sig Process 116 , 1–3 (2023). https://doi.org/10.1007/s10470-023-02184-6

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Emerging VLSI Trends in 2023

by Maven Silicon
July 19, 2023
3 minutes read

Looking for the latest VLSI trends and VLSI jobs in 2023? Maven Silicon, a leading VLSI training institute, is here to guide you. VLSI is revolutionizing industries with its ability to integrate millions of transistors onto a single chip. In this blog post, we’ll explore the emerging VLSI trends in 2023 that are shaping the future and highlight the exciting job openings in this field. Discover the benefits of pursuing a career in VLSI and how Maven Silicon can help you kick-start your journey.

VLSI Application & Trends in 2023

The applications of VLSI span across various industries, including telecommunications, automotive, healthcare, and artificial intelligence. As we move into 2023, several VLSI trends are making waves:

AI-driven VLSI

Artificial Intelligence (AI) has merged with VLSI, opening up endless possibilities. AI-driven VLSI solutions have gained significant traction in industries like autonomous vehicles, robotics, smart homes, and beyond. The integration of AI algorithms directly into VLSI chips allows for the real-time processing of massive amounts of data, leading to intelligent decision-making and unprecedented levels of efficiency. This trend empowers autonomous vehicles to analyze complex surroundings, robots to navigate dynamically changing environments, and smart homes to adapt to residents’ preferences seamlessly. The synergy between AI and VLSI has propelled us toward a new era of intelligent and responsive technologies.

IoT and VLSI

The Internet of Things (IoT) revolution is in full swing, and VLSI plays a pivotal role in shaping this interconnected ecosystem. Emerging trends in VLSI focus on designing chips optimized for IoT-enabled devices, ensuring efficient data communication, low power consumption, and enhanced security. These specialized VLSI chips enable IoT devices to communicate seamlessly over the internet, exchanging data with other devices and cloud services. Moreover, with advancements in low-power design techniques, IoT devices can operate for extended periods on battery power, making them more practical and environmentally friendly. VLSI’s contribution to IoT is driving the proliferation of smart homes, smart cities, and industrial automation, transforming the way we interact with our surroundings.

Edge Computing and VLSI

Edge computing has emerged as a game-changer in handling real-time data processing and analysis. VLSI’s role in this trend is crucial, as it enables the development of high-performance, energy-efficient chips tailored for edge devices. By processing data locally at the edge, these VLSI chips significantly reduce latency and response times, making them ideal for applications that demand immediate results. Edge devices, such as sensors and cameras, benefit from low-power VLSI solutions that allow for prolonged operation without compromising performance. The combination of edge computing and VLSI has unlocked a new realm of possibilities, from responsive AI applications to smart infrastructure like traffic management and environmental monitoring.

Benefits of VLSI

Exciting and challenging work.

The field of VLSI indeed provides a dynamic and intellectually stimulating work environment for engineers and professionals. As a VLSI engineer, you get the opportunity to be at the forefront of designing complex integrated circuits that power a wide range of electronic devices, from smartphones and computers to IoT devices and automotive electronics.

Lucrative Job Opportunities

The demand for VLSI professionals is on the rise, making it a highly sought-after field with numerous job opportunities across various industries. As technology continues to advance and electronic devices become an integral part of our lives, the need for skilled VLSI engineers has grown significantly.

Positions such as VLSI Design Engineer, Verification Engineer, and Physical Design Engineer are in high demand. VLSI Design Engineers are responsible for designing and architecting integrated circuits, while Verification Engineers focus on validating and testing chip designs. Physical Design Engineers, on the other hand, play a crucial role in implementing the circuit layout to optimize performance and power consumption.

Also read: Skills required to become a VLSI engineer?

Job Openings

If you’re eager to embark on a VLSI career, numerous job openings await you. Maven Silicon is renowned for its VLSI training with 100% placement assistance. Explore exciting roles like VLSI Design Engineer, Verification Engineer, Physical Design Engineer, FPGA Engineer, and Analog/Mixed-Signal Design Engineer.

Also read: Salary of VLSI Engineers in India

As we step into 2023, the world of VLSI presents abundant opportunities. Stay updated with the latest VLSI trends, leverage the benefits of this field, and secure a rewarding career in VLSI. Maven Silicon can equip you with the necessary skills to excel in the ever-evolving VLSI landscape. Start your journey towards a successful VLSI career today with our job-oriented courses .

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Why should i do vlsi training.

All the Integrated Chips we use in mobiles, TVs, computers, satellites, and automobiles, etc. are designed with VLSI technology. Hence, there is a huge scope and growth in the VLSI Industry and it is full of job opportunities. Since there is a huge gap between what the college education offers and the industry expectation, it is recommended to go for the VLSI training which bridges that gap and gives you a great hands-on experience.

What is chip designing?

Steps involved in Chip design Chip’s architecture: Create circuit designs, Run simulations, Supervise layout, Tape out the chip to the foundry and Evaluate the prototype once the chip comes back from the laboratory. Chip designers work to make faster, cheaper and more innovative chips that can automate parts or the entire function of electronic devices. A chip design engineer’s job involves architecture, logic design, circuit design and physical design of the chip, testing, and verification of the final product.

Is VLSI a good career?

VLSI is a very good domain to build a career with a huge number of opportunities. There is a demand for chips in every sector, be it automobiles, consumer electronics or high-end servers. You should have good command on Verilog, SystemVerilog, and UVM to start your career as VLSI Design or VLSI Verification Engineer

What is the eligibility for VLSI Chip Designing Courses?

The undergraduates, graduates, or postgraduates from below streams can take up VLSI Chip Design Course and make a career in VLSI Industry. BE/BTech in EEE/ECE/TE or ME/MTech/MS in Electronics/MSc Electronics

To join the industry as a VLSI verification engineer, you must have hands-on experience of below topics: SystemVerilog, Universal Verification Methodologies UVM, Assertion based Verification SVA

Maven Silicon provides the best quality VLSI training through a variety of design and verification courses to suit your need and demand. We offer online VLSI courses, Job-oriented fulltime and Blended VLSI courses, Internship programs, part time courses and corporate training.Explore our offerings at https://www.maven-silicon.com/

Every course has a different admission procedure: 1. For Advanced VLSI Design and Verification course at Maven Silicon, you can apply while you are in the final semester, graduation or post-graduation. 2. For the Internship program, you can apply in your pre-final/final year. Advise you to book your seats in advance, pertaining to limited admissions and increased demand. 3. You can subscribe to our online courses directly from our elearn portal https://elearn.maven-silicon.com/ You can apply for our Online, Job-oriented, Part-time and Corporate courses on https://www.maven-silicon.com/application

We do have an entrance exam for our job-oriented courses VLSI RN and VLSI VM. After you meet the eligibility criteria you have to undergo an Online Entrance Test which would check you on the concepts of Basic Electronics and Digital Electronics. Post scoring 60% in this test, you are processed for the technical interview with our technical experts. Based on your performance during the interview, you will be selected for the Advanced VLSI Design and Verification course. For our online VLSI courses, we do not have any entrance exams. You can directly subscribe the courses from our elearn portal https://elearn.maven-silicon.com/

Yes, we do provide the scholarship on our job-oriented courses VLSI RN and VLSI VM based on your performance in the technical interview. To excel in the Online entrance test and the technical interview, we suggest you take our Online Digital electronics course at https://elearn.maven-silicon.com/digital-electronics This online Digital electronics course will help you to learn and refresh the complete fundamentals of digital electronics, highly needed for any VLSI course. Contact us for more details.

We provide 100% placement assistance with our job-oriented course until you get placed. You can refer the link for the placement updates and know more about our hiring partners: https://www.maven-silicon.com/placement

VLSI Frontend course imparts training in the Design and Verification of a chip which mostly includes RTL(Register Transfer Level) coding using either VHDL/Verilog/SystemVerilog and the verification of the DUT(can be an IP or SOC) by building verification Environment or Testbench using SystemVerilog/UVM/.You also learn to meet the timing constraints of the chip using STA(Static Timing Analysis) and Synthesizing the design using synthesizable constructs. The maximum number of VLSI job opportunities are available in the Verification segment. Backend courses mostly deal with the physical design part of the chip which includes Floorplan, Map, Place and route and DFT and ATPG scan insertion and checks for the flip flops. It also includes the physical verification part of the chip, memory characterization, analog layout, and design.

Yes. VLSI is a high growth domain with huge job opportunities. Electronics is the basic knowledge required to get into the VLSI industry. Engineers with Electronics background can enter into VLSI Industry easily. The VLSI Course is helpful for ECE/EEE students to learn and build up the skill set as per the Industry requirement to enter the Chip/IC Design and Verification Domain.

Inexpensive courses with the utmost quality are our unique selling points. You can explore our courses at https://elearn.maven-silicon.com/

We help you with support material to enhance your basic knowledge of Digital electronics and perform your best. Our online Digital electronics course will help you to learn and refresh the complete fundamentals of digital electronics, which are highly needed for any VLSI course. Contact us for more details.

We do have online VLSI courses for engineers like you. You can start learning with our hands-on online VLSI courses which comes with labs, project, reference material. We also connect with live Q&A, doubt clarification sessions and Whatsapp support group. Click here to explore and subscribe https://elearn.maven-silicon.com/ . If you are looking for online VLSI course with Placement support, then you refer our Blended VLSI learning program at https://www.maven-silicon.com/blended-vlsi-design-asic-verification

We always encourage you to join the course along with friends because it motivates you to learn and finish the course at a fast pace. Contact us to know about group discount options.

Yes. It is good to start early. You can explore and subscribe to our online VLSI design methodologies course or our Internship Program. It is a front-end VLSI course that imparts the VLSI Design Flow, Digital Design and RTL programming using Verilog HDL. After completing the online VLSI DM course/Internship Program, you can easily crack college campus interviews or you can also take up our Advanced ASIC Verification course with 100% placement assistance and can avail up to 100% scholarship based on your grades in our Online VLSI Design Course and the scores of technical interview with our experts.

Yes, we have part-time/Weekend VLSI courses for working professionals. They are specially designed to help you strike a balance between your job and learning. Explore VLSI DM and VM part-time course under Part-time VLSI course in Program offerings at our website https://www.maven-silicon.com/systemverilog-uvm-functional-verification-course

Our Job oriented VLSI courses are highly effective and rigorous programs and follow a continuous evaluation scheme. Candidates are evaluated in the courses through lab reports, project reports, practice tests, assignments, technical presentations, and mock interviews. We also have an evaluation program in our Online VLSI courses through quizzes, tests, and assignments.

You do not need to pay extra for the requisite learning material. We do provide free library access and free online VLSI Courses to our trainees enrolled for job oriented courses for reference and support.

Once you complete your online VLSI course you can upgrade to job oriented VLSI Courses with a very good scholarship. We provide 100% placement assistance for the job oriented VLSI Courses. Advanced VLSI Design and Verification [VLSI – RN ] and Advanced ASIC Verification [ VLSI-VM ] are the job oriented VLSI Courses.

Maven Silicon offers customized in-house and onsite corporate VLSI training courses. This program is specially designed for engineers keeping in view the ever-changing demands of the industry. The participants are equipped with the latest tools, techniques, and skills needed to excel as Verification Engineers. Some of our Corporate training VLSI Courses are SystemVerilog HVL, Verilog HDL, Universal Verification Methodology and Assertion based Verification. Click here for more details: https://www.maven-silicon.com/corporate-training

Yes. Our courses will be very useful. We have had many students taking up our course before going to foreign universities for their Master’s program in VLSI. The practical approach of the courses could help them get campus job opportunities and assistantships..

You can opt for online or offline course but you must choose the right mode considering the time you can spend and the flexibility you need. The online course also provides you Live Q&A, doubt clarification, handy technical support and reference material. So, it is a great offering with best of both worlds. You can learn on the go along with your college studies/ regular office hours and upskill yourself. With Maven Silicon’s Online Verification course, you can master VLSI even if you stay in a remote corner of the world.

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Best VLSI based IEEE project topics for engineering students

Long gone are the days wherein computers are as large as rooms with large vacuum tubes. They no longer take up an entire room or make loud humming noises. All these operations have scaled-down in size and multiplied in application. Nowadays, we see products that occupy very little space but offer abundant functionality. Modern-day machines get smaller in size and larger in an application, every single day. So, what pushed this technology forward by such a large extent? The art of computing brought in a wave of electronic miniaturization thanks to the semiconductor transistor. One of the most important fields that work closely with this is VLSI technology. If you are a budding EEE engineer, then VLSI projects are something you need to invest time and energy in. Here’s a look at some great VLSI IEEE projects to help you get started on your journey

Have you checked out our projects on VLSI yet? VLSI Kit will be shipped to you and you can build using tutorials. You can start with a free demo today!

1. VLSI Starter

2. VLSI Explorer

3. VLSI Champion

4. VLSI (Career Building Course)

Discover more IEEE VLSI projects

What is a VLSI design?

VLSI stands for Very Large-Scale Integration. Essentially, this involves the creation of integrated circuits by combining thousands of MOS transistors and other electrical components onto a single chip. These MOS IC chips are a staple within the electronics industry and enabled complex semiconductor, signal processing and communication technologies to come up. VLSI design consists of all the different processes that go into creating these IC chips.

Explore more IEEE VLSI projects

Processes Involved in Designing a VLSI IC

Front End Steps:

Problem Specification - Represent the system in a mainframe by defining the performance characteristics and other definitions.
Architecture Definition - Define what architecture you will use, number of floating point units, RISC or CISC, and what cache size.
Functional Design - Once the architecture is chosen, decide the facilitates to be provided. Also, functionalities it should have, and the specifications of the functional units.
Logic Design - Integrate boolean expressions, control flow, register allocation and RTL description.
Circuit Design - Create a circuit as a netlist, containing gates, transistors and other important components.
Physical Design - Convert the netlist into a physical body as a layout. This is done by the following protocol called the lambda rules which details the size, ratio and spacing of components.

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Want to develop practical skills on VLSI? Checkout our latest projects and start learning for free

Back end Steps:

Wafer processing - Melting of silicon and then inserting the crystal orientation is called wafer processing. After this, the polishing of the ingot and crystal orientation occurs.
Lithography - Mask with a photographic mask and highlight tracks on it by exposing it to UV lights.
Etching - This step helps in removing material selectively so as to create patterns, by using additional chemicals or plasma.
Ion implantation - Add the necessary dopants as ions in a targeted manner.
Metallization - Deposit a thin layer of aluminum over the wafer to act as a good conductor.
Assembly and Packaging - Cut the wafer into single chips, separate them and then test them individually. After ascertaining that they are of high quality, package them as needed.

Explore more about VLSI design

Skyfi Labs helps students develop skills in a hands-on manner through VLSI Online Courses where you learn by building real-world projects.

You can enrol with friends and receive kits at your doorstep.

You can learn from experts, build working projects, showcase skills to the world and grab the best jobs. Start Learning VLSI today!

What is VLSI and its applications?

VLSI chips are used in all kinds of fields. Some examples include;

Personal computers, cell phones, digital cameras
Consumer electronic gadgets.
Automobiles and Anti-Lock Braking Systems
Medical field, medical equipment
Digital signal processing
Speech identification and translation
Switching telephone circuits
Voice communication networks
Data networks

Advantages of VLSI Technology

Smaller sized components as circuit elements form single chips
Lower cost thanks to the power of mass production
Lower power consumption due to smaller size
Higher reliability as there are fewer interconnections
Additional functionality
Efficient use of space
Reduced weight and easier packaging
Easily replaceable
High operating speeds
Significant career and growth opportunities

Online VLSI design courses for engineering students

VLSI Starter online course for engineers

Everything from smartphones to complicated aircraft makes use of VLSI technology in some way or the other. This VLSI design course will serve as the best introductory course, as it opens you to the subject. Since the VLSI industry is worth 1.75 trillion dollars, this is a great opportunity for you to further your career. In this online course, students will learn how to work with industry-wide tools, such as Xilinx ISE and to program in Verilog. The students will also be working with Logic Gates, comparators, encoders and decoders.

Explore more about this course

VLSI Explorer online course for engineers

This is the perfect VLSI IEEE project if you are a medium-level user of VLSI technology. This course will help you understand more about how the technology works. It is perfect for understanding the widespread applications of technology. Furthermore, this course gives students an opportunity for hands-on experience. They get to work with the actual codes and simulations and get a solid introduction to VLSI. They also learn Verilog Programming, work with logic gates and build circuits with the help of this course.

Learn more about this course

VLSI Champion online course for engineers

In case you already know about the basics of VLSI, this is the course to take to improve your knowledge. By the end of this VLSI IEEE project, students will gain experience with tools like Xilinx ISE. They will also gain exposure to the creation and development of combinational and sequential circuits. Students will model electronic systems, and design in the Xilinx Design Suite. They will gain an insight into Verilog Programming, optimization and learn how to build a Static RAM Design.

Discover more about this VLSI course

Best VLSI-based IEEE projects for engineering students

1. Real-time Traffic Light Control

In this VLSI design IEEE project, students will learn how to build an FPGA-based traffic light controller. Not only does this help regulate traffic, but it also reduces the average waiting time of drivers. Since VHDL can help simulate the working of circuits, it is used to build this interface. A model of the controller is created using VHDL, and to verify the design, a timing simulation is done. By taking part and completing this project, students will gain a thorough understanding of how VLSI technology works.

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2. Fuzzy-based PID controller

This VLSI IEEE project is extremely useful and has many applications in the transportation industry. In order to create this system, we interface Fuzzy Logic Controllers, MATLAB and the VLSI system. The programming is done in the VHDL language. In effect, the PID controller works as a great feedback control mechanism. It finds use in flight controllers, high-speed trains, motor drivers, and even for water regulation. Therefore, this project brings EEE engineers the best of both worlds. It has equal parts of fuzzy logic, and VLSI technology, making it a great project to learn a lot of new skills.

Learn more about this IEEE project

3. Design and VLSI implementation of Anti-collision robot processor

Robots are occupying this world faster than ever. In manufacturing industries multiple robots have to work in the same environment this IEEE project helps you to design a robot processor that detects and avoids the other robots with the help of RFID technology. As part of this VLSI project, you will be introduced into the VLSI design process.

Find more IEEE VLSI projects from the following list:

Behavioural synthesis of Asynchronous circuits
Design of FPGA based 32-bit Floating-point Arithmetic unit
Design and synthesis of QPSK
Design of CAN protocol
Fuzzy based mobile robot controller designing using VHDL
Implementation of Highspeed pipeline VLSI Architecture
Implementation of overlap based logic cell and its power analysis
Design of data encryption standard for data encryption
ASIC Design of complex multiplier

The field of engineering is extremely competitive. Therefore, to differentiate yourself from the crowd and really enhance your value, you need to constantly upskill. When you look at the field of EEE, VLSI technology is a very impactful and useful area. By taking part in these VLSI IEEE projects, you get to build experience and learn valuable concepts to come out as a better engineer.

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List of topics.

SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) is a journal that publishes articles which contribute new novel experimentation and theoretical work in in all areas of VLSI & Signal Processing and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical VLSI & Signal Processing.

VLSI Circuits
Computer-Aided Design (CAD)
Low Power and Power Aware Design
Testing, Reliability, Fault-Tolerance
Emerging Technologies
Post-CMOS VLSI
VLSI Applications (communications, video, security, sensor networks, etc.)
Nano electronics, Molecular, Biological and Quantum Computing.
Intellectual property creating and sharing.
Wireless communications.
Custom, semi-custom, ASIC, programmable circuit design.
Performance-driven, reliability-driven, thermally-driven, radiation hardening design.
Processor, co-processor, multi-processor, memory design.
Digital, analog, RF, mixed, asynchronous circuit design.
Transducer design.
Design for testability, built-in self-test.
Adaptive Computing Systems with FPGA components.
Mixed Analog / Digital Systems.
Technology-related design, interconnect design, very deep submicron design
Signal processing theory, algorithms, architecture, design, and implementation.
Image / video processing, coding, compression, restoration, analysis, understanding, and communications.
Speech processing, coding, compression, and recognition.
Audio signal processing, coding, and compression.
Image/video processing, coding, compression, restoration, analysis and understanding, and communications.
Multimedia signal processing and technology.

Any other topics relevant to latest trends in VLSI & Signal Processing.

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Get started with your final year engineering projects with us. We are creators of a unique and innovative project Making platform for engineering students, which helps them to gain the real time experience and get the creative mind as well. We offer highly skilled VLSI and Matlab projects for engineering students. We are committed to providing the best VLSI projects and bridging the gap between academic and practical exposure within the engineering students and making them best engineer’s.

IEEE Projects for VLSI 2023 – 2024 Titles

Explore the latest IEEE VLSI projects and Machine Learning Projects for students and researchers. Our wide range of topics includes design and implementation of digital circuits, low power VLSI, FPGA and ASIC design, VLSI testing and verification, and more. Learn and advance your skills with our comprehensive project descriptions and resources.

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5. party identification among religious groups and religiously unaffiliated voters.

The relationship between partisanship and voters’ religious affiliation continues to be strong – especially when it comes to whether they belong to any organized religion at all.

Bar charts showing party identification among religious groups and religiously unaffiliated registered voters in 2023. As they have for most of the past 15 years, a majority of Protestant registered voters (59%) associate with the GOP. And 52% of Catholic voters identify as Republicans or lean toward the Republican Party, compared with 44% who identify as Democrats or lean Democratic. Meanwhile, 69% of Jewish voters associate with the Democratic Party, as do 66% of Muslims. Democrats maintain a wide advantage among religiously unaffiliated voters.

The gap between voters who identify with an organized religion and those who do not has grown much wider in recent years.

Protestants mostly align with the Republican Party. Protestants remain the largest single religious group in the United States. As they have for most of the past 15 years, a majority of Protestant registered voters (59%) associate with the GOP, though as recently as 2009 they were split nearly equally between the two parties.

Partisan identity among Catholics had been closely divided, but the GOP now has a modest advantage among Catholics. About half of Catholic voters identify as Republicans or lean toward the Republican Party, compared with 44% who identify as Democrats or lean Democratic.

Members of the Church of Jesus Christ of Latter-day Saints remain overwhelmingly Republican. Three-quarters of voters in this group, widely known as Mormons, identify as Republicans or lean Republican. Only about a quarter (23%) associate with the Democratic Party.

Trend charts over time showing that Protestants remain solidly Republican, and Catholics now tilt toward the GOP.

Jewish voters continue to mostly align with the Democrats. About seven-in-ten Jewish voters (69%) associate with the Democratic Party, while 29% affiliate with the Republican Party. The share of Jewish voters who align with the Democrats has increased 8 percentage points since 2020.

Muslims associate with Democrats over Republicans by a wide margin. Currently, 66% of Muslim voters say they are Democrats or independents who lean Democratic, compared with 32% who are Republicans or lean Republican. (Data for Muslim voters is not available for earlier years because of small sample sizes.)

Democrats maintain a wide advantage among religiously unaffiliated voters. Religious “nones” have become more Democratic over the past few decades as their size in the U.S. population overall and in the electorate has grown significantly. While 70% of religiously unaffiliated voters align with the Democratic Party, just 27% identify as Republicans or lean Republican.

Related: Religious “nones” in America: Who they are and what they believe

Religion, race and ethnicity, and partisanship

Over the past few decades, White evangelical Protestant voters have moved increasingly toward the GOP.

Today, 85% of White evangelical voters identify with or lean toward the GOP; just 14% align with the Democrats.

Trend charts over time showing how race, ethnicity and religious identification intersect with registered voters’ partisanship. Today, 85% of White evangelical voters identify with or lean toward the GOP; just 14% align with the Democrats. Over the past three decades, there has been a 20 point rise in the share of White evangelicals who associate with the GOP. 60% of Hispanic Catholic voters identify as Democrats or lean Democratic, but that share has declined over the past 15 years.

Over the past three decades, there has been a 20 percentage point rise in the share of White evangelicals who associate with the GOP – and a 20-point decline in the share identifying as or leaning Democratic.

Over the past 15 years, the GOP also has made gains among White nonevangelical and White Catholic voters.

About six-in-ten White nonevangelicals (58%) and White Catholics (61%) align with the GOP. Voters in both groups were equally divided between the two parties in 2009.

Partisanship among Hispanic voters varies widely among Catholics and Protestants.

60% of Hispanic Catholic voters identify as Democrats or lean Democratic, but that share has declined over the past 15 years.
Hispanic Protestant voters are evenly divided: 49% associate with the Republican Party, while 45% identify as Democrats or lean Democratic.

A large majority of Black Protestants identify with the Democrats (84%), but that share is down 9 points from where it was 15 years ago (93%).

Party identification among atheists, agnostics and ‘nothing in particular’

Atheists and agnostics, who make up relatively small shares of all religiously unaffiliated voters, are heavily Democratic.

Among those who identify their religion as “nothing in particular” – and who comprise a majority of all religious “nones” – Democrats hold a smaller advantage in party identification.

More than eight-in-ten atheists (84%) align with the Democratic Party, as do 78% of agnostics.
62% of voters who describe themselves as “nothing in particular” identify as Democrats or lean Democratic, while 34% align with the GOP.

Trend charts over time showing that religiously unaffiliated registered voters are majority Democratic, especially those who identify as atheist or agnostic.

Partisanship and religious service attendance

Voters who regularly attend religious services are more likely to identify with or lean toward the Republican Party than voters who attend less regularly.

Trend charts over time showing that Republicans hold a majority among registered voters who regularly attend religious services. Most less-frequent observers align with the Democratic Party.

In 2023, 62% of registered voters who attended religious services once a month or more aligned with Republicans, compared with 41% of those who attend services less often.

This pattern has been evident for many years. However, the share of voters who identify as Republicans or lean Republican has edged up in recent years.

For White, Hispanic and Asian voters, regular attendance at religious services is linked to an increase in association with the Republican Party.

However, this is not the case among Black voters.

Dot plot chart showing that across most Christian denominations, registered voters who attend religious services regularly are more likely than others to align with the GOP. However, this is not the case among Black voters. Only about one-in-ten Black voters who are regular attenders (13%) and a similar share (11%) of those who attend less often identify as Republicans or Republican leaners.

Only about one-in-ten Black voters who are regular attenders (13%) and a similar share (11%) of those who attend less often identify as Republicans or Republican leaners.

Higher GOP association among regular attenders of religious services is seen across most denominations.

For example, among Catholic voters who attend services monthly or more often, 61% identify as Republicans or lean toward the Republican Party.

Among less frequent attenders, 47% align with the GOP.

Black Protestants are an exception to this pattern: Black Protestant voters who attend religious services monthly or more often are no more likely to associate with the Republican Party than less frequent attenders.

Facts are more important than ever

In times of uncertainty, good decisions demand good data. Please support our research with a financial contribution.

Report Materials

Table of contents, behind biden’s 2020 victory, a voter data resource: detailed demographic tables about verified voters in 2016, 2018, what the 2020 electorate looks like by party, race and ethnicity, age, education and religion, interactive map: the changing racial and ethnic makeup of the u.s. electorate, in changing u.s. electorate, race and education remain stark dividing lines, most popular.

About Pew Research Center Pew Research Center is a nonpartisan fact tank that informs the public about the issues, attitudes and trends shaping the world. It conducts public opinion polling, demographic research, media content analysis and other empirical social science research. Pew Research Center does not take policy positions. It is a subsidiary of The Pew Charitable Trusts .

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VLSI & Signal Processing Research Topics
List of Topics. SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) is a journal that publishes articles which contribute new novel experimentation and theoretical work in in all areas of VLSI & Signal Processing and its applications. The journal welcomes publications of high quality papers on theoretical developments and ...
IEEE Projects for VLSI 2023
Explore the latest IEEE VLSI projects and Machine Learning Projects for students and researchers. Our wide range of topics includes design and implementation of digital circuits, low power VLSI, FPGA and ASIC design, VLSI testing and verification, and more. Learn and advance your skills with our comprehensive project descriptions and resources. S.
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VLSI Seminar Topics (vlsi seminar ,latest vlsi seminar topics, vlsi seminar list , vlsi research center , vlsi seminar , vlsi seminar projects, vlsi projects training, m.tech vlsi seminar) Data rendition flip-flops for power down applications On chip ESD protection sgategics for RF circuits in CMOS technologies
Party affiliation of US voters by religious group
Protestants mostly align with the Republican Party. Protestants remain the largest single religious group in the United States. As they have for most of the past 15 years, a majority of Protestant registered voters (59%) associate with the GOP, though as recently as 2009 they were split nearly equally between the two parties.