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problem on clone
By chenyong September 16, 2011 in UVM SystemVerilog Discussions
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I met a problem on clone. In my code for scoreboard, I defined a variable as this:
timer_pkt_item chk_pkt;
the timer_pkt_item is defined as a class in other place. I then register it as:
`uvm_component_utils_begin(timer_scoreboard)
`uvm_field_object(chk_pkt, UVM_DEFAULT)
`uvm_component_utils_end
In my write function for export implementation, I would like to do this:
function void write_pkt(timer_pkt_item rcv_pkt);
chk_pkt = rcv_pkt.clone();
endfunction
My purpose is to save received data of rcv_pkt.
When I start to compile the code, irun reports error as:
assignment operator type check failed (expecting datatype compatible with 'class timer_pkt_item' but found 'class uvm_object' instead). so what is the problem to the code? I think I have defined the variable type as timer_pkt_item, why there is problem? please give me some help. thanks.
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clone() returns a uvm_object, which you need to cast. Your code should be :
$cast ( chk_pkt , rcv_pkt.clone())
- ljepson74 and chandan
yes, you are right. thanks.
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SystemVerilog queue initialization using ncverilog +sv?
Steven Wilson
--- news:// freenews.netfront.net/ - complaints: [email protected] ---
Jonathan Bromley
>I have a question for the assembled masses.
>I have a declaration similar to the following: > >integer my_q[$] = {1,2,3,4,5,6}; > >This is accepted by Modelsim using the -sv switch.
>If I compile this with ncverilog +sv I get the following gripes: > >ncvlog: *E,TYCMPAT ( queue.sv ,5|18): assignment operator type check >failed (expecting datatype compatible with 'queue of integer' but >found 'packed array' instead). >integer my_q[$] = {1,2,3,4,5,6}; > | >ncvlog: *E,NONOWD ( queue.sv ,5|19): Illegal use of a constant without >an explicit width specification [4.1.14(IEEE)]. >integer my_q[$] = {1,2,3,4,5,6}; >etc... > >Any suggestions as to what I'm doing wrong here?
I will try to write up an appnote-style description of unpacked array concatenation somewhere, soon; it's a very useful construct, and deserves to be widely known so that people start demanding it from their vendors. -- Jonathan Bromley
SystemVerilog Mailbox
A SystemVerilog mailbox is a way to allow different processes to exchange data between each other. It is similar to a real postbox where letters can be put into the box and a person can retrieve those letters later on.
SystemVerilog mailboxes are created as having either a bounded or unbounded queue size. A bounded mailbox can only store a limited amount of data, and if a process attempts to store more messages into a full mailbox, it will be suspended until there's enough room in the mailbox. However, an unbounded mailbox has unlimited size.
- Generic Mailbox that can accept items of any data type
- Parameterized Mailbox that can accept items of only a specific data type
SystemVerilog Mailbox vs Queue
Although a SystemVerilog mailbox essentially behaves like a queue , it is quite different from the queue data type. A simple queue can only push and pop items from either the front or the back. However, a mailbox is a built-in class that uses semaphores to have atomic control the push and pop from the queue. Moreover, you cannot access a given index within the mailbox queue, but only retrieve items in FIFO order.
Where is a mailbox used ?
A SystemVerilog mailbox is typically used when there are multiple threads running in parallel and want to share data for which a certain level of determinism is required.
Generic Mailbox Example
Two processes are concurrently active in the example shown below, where one initial block puts data into the mailbox and another initial block gets data from the mailbox.
Note that there is a race between the two threads where the first thread can push into the mailbox and the second thread can pop from the mailbox on the same delta cycle. Hence the value displayed using num() is valid only until the next get or put is executed on the mailbox and may depend on the start and finish times of the other methods.
SystemVerilog Mailbox Functions and Methods
Parameterized mailboxes.
By default, a SystemVerilog mailbox is typeless and hence can send and receive objects of mixed data-types. Although this is a good feature, it can result in type mismatches during simulation time and result in errors. To constrain the mailbox to accept and send objects of a fixed data-type, it can be parameterized to that particular data-type.
In the example shown below, we first create an alias for mailboxes that can send and receive strings using the typedef construct. Although this step is optional, it is a good practice to avoid type mismatches between different components from coding errors. Consider that comp1 sends a few strings to comp2 via this mailbox. Naturally both classes need to have a mailbox handle which needs to be connected together and this is best done at the top level or the module where these two classes are instantiated.
Matching different type mailboxes
Let's see what would have happened if the SystemVerilog mailboxes were parameterized to different data-types. Consider comp1 to have string type and comp2 to have a byte type mailbox.
This would result in a compile time error, and allow us to revisit the testbench code to correct the type mismatch.
IMAGES
VIDEO
COMMENTS
1. The problem is that you are trying to place an instance of your interface where the port list of another interface should be. That is illegal syntax. You want to place the interface instance inside the body of a module. Here is a complete code example which shows 2 instances of your interface which use different parameter values:
A_reg[m][n] = W[(m*M+n)*16+:16]; | ncelab: *E,TYCMPAT (./mult.sv,126|24): assignment operator type check failed (expecting datatype compatible with 'packed array' but found 'unpacked array [15:0] of signed packed array [15:0] of logic' instead). ... *E,TYCMPAT (./mult.sv,146|40): assignment operator type check failed (expecting datatype ...
xmvlog: *E,TYCMPAT (testbench.sv,21|18): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'int' but found 'queue of int' instead). xmvlog: *W,NOTOPL: no top-level unit found, must have recursive instances.
assignment operator type check failed (expecting datatype compatible with 'class timer_pkt_item' but found 'class uvm_object' instead). so what is the problem to the code? I think I have defined the variable type as timer_pkt_item, why there is problem? please give me some help. thanks.
This is accepted by Modelsim using the -sv switch. If I compile this with ncverilog +sv I get the following gripes: ncvlog: *E,TYCMPAT ( queue.sv ,5|18): assignment operator type check. failed (expecting datatype compatible with 'queue of integer' but. found 'packed array' instead).
In reply to cgales:. Thanks a lot. I know the mistake i did. I created a different queue of int type and then made the assignment. It worked !!
SystemVerilog AMS simulation (ADE) xmelab ERROR, TYCMPAT: port or terminal connection type check failed on instance (expecting datatype compatible with 'packed array' but found 'unpacked array[0:1] of packed array [3:0] of logic' instead) ADJK over 1 year ago.
In reply to son la:. Thank you very much. A follow up question: should most "regular" arrays declared as unpacked array?
%p is a pretty-print format that uses an assignment pattern as its format. It is using using a signed decimal format for each number. SystemVerilog has arrays-of-arrays. You have declared an array with two elements, and each element has an array with four elements. %h is an unsigned radix format.
The original answer was right. The problem is in the declaration of the agent_m array. Because each instance of the parameterized agent is of a different width, each is a completely different type according to SystemVerilog rules. The declaration: agent agent_m[3]; declares an array of 3 handles to agent#(32) class objects.
In reply to dave_59:. Thanks for your prompt response Dave. There is nothing much than this to show. It is a simple uvm_analysis_imp with a write function the only message that it receives is of the datatype time.
This code creates an error: assignment operator type check failed (expecting datatype compatible with 'int' but found 'queue of int' instead). What is the correct way to find the min and max of this type of array?
SystemVerilog Polymorphism. Polymorphism allows the use of a variable of the base class type to hold subclass objects and to reference the methods of those subclasses directly from the superclass variable. It also allows a child class method to have a different definition than its parent class if the parent class method is virtual in nature.
I have a coverage instantiated in my monitor. I tried to pass a transaction from the monitor to the coverage but I'm having this error: assignment operator type check failed (expecting datatype compatible with 'class uvm_pkg::uvm_analysis_export#(.T(class sent_agent_pkg::packet))' but found 'class uvm_pkg::uvm_analysis_imp#(.T(class sent_agent_pkg::packet),.IMP(class uvm_pkg::uvm ...
A SystemVerilog mailbox is a way to allow different processes to exchange data between each other. It is similar to a real postbox where letters can be put into the box and a person can retrieve those letters later on. SystemVerilog mailboxes are created as having either a bounded or unbounded queue size. A bounded mailbox can only store a limited amount of data, and if a process attempts to ...
p++; counter++; } This appears to be what I want which means I need the assignment operator but I am a bit confused as to what to put in it and I am getting stack overflow errors, here is what I thought I needed to do: ClassA ClassA::operator =(const ClassA& source) {. ClassA* newObject; newObject = new ClassA;
In reply to Muthuvenkatesh:. Because AVERY_AHB_UVM or AVERY_AHB_OVM macro is defined but you didnt pass any value to 'parent' parameter of new function. Either you pass value to parent or you can set default value for 'parent' (null for example) and call:
typedef bit [7 :0] my_type []; defines my_type as a two-dimensional array. my_type my_array []; defines an array of two-dimensional arrays --> a 3-dimensional array. As a result, neither of your assignment works in any of the methods. Method 1 would work if you either remove the last [] in typedef or from declaration: my_type my_array;.
In reply to ncui:. Section 7.2.2 of the LRM specifies how to assign data to a structure. When you use brackets, you are concatenating the values. You need to prefix with a ' to indicate positional assignment: