set_case_analysis synthesis

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Constraining Logically Exclusive Clocks in Synthesis

This is article-5 of how to define Synthesis timing constraint

Logically exclusive clocks are active in the design but cannot interact with each other. When dealing with logically exclusive clock, one often sees a mux with the select line determining which clock is active. An important guideline to remember while dealing with logically exclusive clocks is that logically exclusive clocks shouldn’t interact outside the mux.

Consider the example shown in Figure 1, we have two clocks – CLKA and CLKB that are muxed, such that the design either operates either at CLKA or at CLKB. The user has the option to use a set_case_analysis constraint and apply a value of 0 or 1 to choose either between CLKA or CLKB; if this is done, then for timing analysis only the selected clock will be used by the synthesis tool. However if the select port is unconstrained, then both clocks are allowed to reach both the flip-flop’s clock pin, and either of the two clocks can be independently used as launch or capture clock edges, so the timing analysis will consider all the possible combination for worst case timing; in other words, muxed clocks are not inferred as exclusive clocks automatically for timing analysis. As a result, the synthesis optimization will consider all the following four cases –

Of course, the two middle cases can never happen. So, to direct the synthesis tool to consider only CLKA → CLKA and CLKB → CLKB and to optimize the worst of those two cases only, we need to use –

set_clock_groups -logically_exclusive -group CLKA -group CLKB

By doing this the delay between the two registers will be optimized for the worst of CLKA → CLKA or CLKB → CLKB

Note: Alternatively, we can also apply two false paths for this case – set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB] set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA]

Consider the example shown in Figure 2, where the clocks interact outside the mux. If we use the constraint “set_clock_groups -logically_exclusive -group CLKA -group CLKB”, then the synthesis tool will consider only CLKA → CLKA and CLKB → CLKB will optimize the combination logic for the worst of those two cases only. But there is possibility that the data being launched in flop-3 at CLKA and being captured at flop-2 at CLKB is the worst-case scenario and therefore the combinational logic should be optimized accordingly.

Therefore, we need to create generated clocks for CLKA and CLKB, at the output of the mux –

create_generated_clock -name -CLKA_GEN -source CLKA [get_pins clk_mux/out] create_generated_clock -name -CLKB_GEN -source CLKB [get_pins clk_mux/out]

Then only we need set the two generated clocks as logically exclusive –

set_clock_groups -logically_exclusive -group CLKA_GEN -group CLKB_GEN

Consider the example shown in Figure 3, there are two pairs of clocks that are being independently muxed. CLKA and CLKB is controlled by SEL1 and CLKC and CLKD is controlled by SEL2. Notice that inside our design, the flops that are driven by CLKA or CLKB that communicate with flops being captured by CLKC or CLKD and vice-versa.

To constrain this design, we create two separate logically exclusive clock groups –

set_clock_groups -logically_exclusive -group CLKA -group CLKB set_clock_groups -logically_exclusive -group CLKC -group CLKD

And the delay of each path will be optimized for the worst of the logically possible timing conditions.

Note: Alternatively, we can also apply four false paths for this case – set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB] set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA] set_false_path -from [get_clocks CLKC] -to [get_clocks CLKD] set_false_path -from [get_clocks CLKD] -to [get_clocks CLKC]

Consider the example shown in Figure 4, we have made one small change compared to the example shown in Figure 3; notice that the select line of the muxes, instead of being independent are now connected to each other.

Here we need to create a logically exclusive group between groups containing CLKA & CLKC and another containing CLKB & CLKD –

set_clock_groups -logically_exclusive -group “CLKA CLKC” -group “CLKB CLKD”

Clocks within the group can communicate with each other but clocks across groups cannot. So here CLKA and CLKC can talk to each other but neither CLKA nor CLKC can communicate to CLKB or CLKD (or vice versa).

Note: It will take eight different set_false_path commands to accomplish the same thing that we can do using one set_clock_groups command

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VLSI SoC Design: Concepts, Perspective & Implementation

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April 24, 2018

False path v/s case analysis v/s disable timing.

• Some latest tool versions also support a case value of static which means that the node will always be static (never toggle), and this is used to reduce the pessimism which doing noise analysis.
• Case analysis is also particularly useful for DFT modes where you would want to set a few configuration registers and drive the chip into a particular DFT mode: like atspeed, shift or stuck-at mode. This acts as an additional level of verification because you'd expect to see only scan chains in the shift mode with scan enable being 1. You'd expect to see functional paths in the atspeed mode with scan enable being X, and you'd expect to see only paths ending at functional register inputs in the stuck-at mode with scan enable being 0.

4 comments:

What does it mean when you say "For example if you have a MUX based divider"? What sort of divider are you talking about? Please reply

Hi Naman, In first example , lets name the flop below flop B as H. Now is there any valid timing path between flop H and flop G?

So does this mean that in all the 3 cases above,the tool will fix or try to fix max cap, max fanout and max slope?

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Design Constraints

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Design constraints are ASIC design specifications that are applied during synthesis (RTL to netlist), physical design, as well as STA. Each EDA tool attempts to meet these design constraints during the design’s implementation process. These design constraints could be categorized as:

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Bibliography

P. Kurup, T. Abbasi, Logic Synthesis Using Synopsys (Kluwer Academic Publishers, Dordrecht, 1995)

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Golshan, K. (2020). Design Constraints. In: The Art of Timing Closure. Springer, Cham. https://doi.org/10.1007/978-3-030-49636-4_3

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Static timing analysis (sta) concepts.

• In a latch, one edge of the clock makes the latch transparent, that is, it opens the latch so that output of the latch is the same as the data input;this clock edge is called the opening edge.
• The second edge of the clock closes the latch, that is, any change on the data input is no longer available at the output of the latch; this clock edge is called the closing edge.
• The unique property which enables above advantages is time borrowing.
• A level-sensitive latch is transparent for the duration of an active clock pulse. Time borrowing technique can relax the normal edge-to-edge timing requirements of synchronous designs.
• A combinational path which is long enough and is determining the maximum frequency of the design can borrow some time from a shorter path in subsequent latch-to-latch stages to meet its timing.

• Operating Conditions
• Multi voltage and power optimization constraints
• wire load models
• system interface
• design rule constraints
• timing constraints
• area constraints
• timing exceptions
• logic assignments
• Near to capture path.
• Because there may be other paths passing through or originating from the flop nearer to launch flop. Hence buffer insertion may affect other paths also. It may improve all those paths or degrade. If all those paths have violation then we may insert buffer nearer to launch flop provided it improves slack.
• Pin Swapping
• Cell Sizing
• Logic Restructuring
• Cloning is a method of optimization that decreases the load of a heavily loaded cell by   replicating the cell.
• Buffering is a method of optimization that is used to insert buffers in high fan-out nets to decrease the delay
• HFN's are the nets which drives more number of load as compared to other nets. we set some   max fan out limit by using set_max_fanout.
• The nets which have greater than these limits are considered as HFN's.
• Example Clock, Set/Reset, Scan Enable nets are high fan-out nets.
• Logic restructuring means to rearrange logic to meet timing constraints on critical paths of design.
• Move high switching operations up in the logic cone and low switching operations back in the logic cone; a gate-level dynamic power optimization technique.
• In design with low-power intent, synthesis tools automatically perform a variety of power optimization techniques including logic restructuring.
• It reduce three stages to two stages through logic equivalence transformation, so the circuit has less switching and fewer transitions.
• On a sample of designs, logic restructuring reduced dynamic power by less than 5%. It had no significant impact on any other aspects of the design flow.
• Setup time: Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data is reliably sampled by the clock.
• Hold time: The hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data is reliably sampled by the clock.
• Clock to Q delay: The clock to Q delay is the amount of the propagation time required for the data signal to reach the output (Q) of the flip flop after the clock event.
• set library path
• read the design
• link library and the design
• add design constraints (read_sdc)
• add constant value to input port (for timing simulation)
• report_constraints
• report_timing
• Input Transition Time
• Output Load Capacitance
• Parasitic Capacitance
• Resistance of net
• Negative Setup time: In certain cases, due to the excessive delay (example: caused by lot of inverters in the clock path) on the clock signal, the clock signal actually arrives later than the data signal. The actual clock edge you want your data to latch arrives later than the data signal. This is called negative set up time.
• Negative Hold time: It basically allows the data that was supposed to change in the next cycle, change before the present clock edge.

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Sunday, February 6, 2011

Synopsys design constraints (sdc) basics, 31 comments:.

This comment has been removed by the author.

Nice post. Please keep up the good work. If time permits, please visit http://eda-automation.blogspot.com I copied your post(SPEF & related) & posted in my blog. I hope that you won't have any problem as I kept your blog as a source. Please let me know incase if you want me to remove the post. My mail id is [email protected]

Kumar I have no problem ... But I will suggest you that in place of mentioning the link in the last please mention in the starting. Another comment I didn't get??

Thanks for the reply. I'll do that from next time onwards. The same comment appeared twice, so I deleted one. Can I've your g-mail id? Would like to be in touch through mails.

My mail id is: [email protected]

Hi, Starting with SDC version 1.9, you can use "-comment" option with a few SDC commands to include user-specific comment. The comment string associated with the specified command is written out when you use write_sdc or write_script command. The following example shows how to use the -comment option: create_clock -period 10 [get_ports CLK] -comment "for block1.rev0 in Test Mode"

thanks pallavi- for this info.

Respected Sir, I have used virtual clock for constraining I/Os. Referring one document related to Time-Quest Analyzer I have made .sdc file. First I have made one base clock which is given to FPGA and made one virtual clock same freq as base clock. In my design there are 4 base clocks. So for unrelate those clocks I have used set_clock_group constraint. As I have not add any virtual clock in that constraint, got negative slack for that. What is the reason behind it? I couldn't understand. If I put those virtual clocks in that constraint then I will get positive slack.

Respected Sir, I got one more difficulty. I have added set_clock_group constraint inside the .sdc file. In that I have made one clock group including PLL input clock and output clocks. As per my understanding these all clocks are related and that is also happens. Timequest will count the timing between those clocks. Now I got negative slack for setup and hold relationship with launch clock as PLL-clock1 and PLL input clock as latch clock. What will be the possible solution for this. Should I use multicycle constraint in this scenario?

Hello, Can anyone give the answer for above questions?

Hi, Sorry For late reply.. that depends. If the two clocks are related -- then the edges will be related. And then MCPs might not be appropriate. So first things to be answered: 1. Are the two clocks related. If yes, what is their relationship? (divide by 4, divide by 3, etc) 2. Is the path being reported...a genuine multi cycle? This is specific to each design and a general answer cannot be given.

What is the sdc command to specify that, the skew balancing is not required for set of flops or for a clock

You need to add those pins in the exclude pins part ( CTS Spec file)

i m working in chicago as an IC Design intern. I came across a problem, we have a port named errin1. It is present in 2 different blocks and one block has clk as clock and other has clkport for clock signal. In sdc file how do I differentiate this for mentioning delay for two clocks for same port.

Thank you so much.

This comment has been removed by a blog administrator.

Thank you so much for all the tips!!!

Hi, Could you clarify on when I should write SDC and in what cases I let the tool generate it ? My understanding is, I specify my target clock period to the tool using a constraint and ask the tool to optimize the netlist if possible to match that period. In that case, why will I need the tool to write the SDC for me ? Thanks

what is the syntax i suppose to use for don't optimize the buffer delay between the nodes

I have one doubt regarding input delays specified in SDC's. Initially in sdc some input delays are specified,but after Cts and before OptCts input delays are changing. could you please explain,why the input delays are changing

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Must Read Article

STA Basics - kkanthan77/Static-Timing-Analysis GitHub Wiki

Static timing analysis.

• Analysis of the design for timing issues
• STA provides a faster and simpler way of checking and analyzing all the timing paths in a design for any timing violations.

Modelling of a gate level netlsit

STA can be modeled for the following reasons

• How the interconnect is modeled - Ideal interconnect, wire load model, global routes with approximate RCs, or real routes with accurate RCs
• How clocks are modeled - ideal or propagated
• Whether coupling between signals is included - whether any cross-talk noise is analyzed or not

Clock Uncertainity

Clock latency, generated clocks.

a. Clock which is derived from the master clock.

• If there's a /3 circuitry, once would define a generated clock definition at the output of this circuitry
• Definingn a new clock as generated clock doesn't create a new clock domain and the generated clock is considered to be in phase with the master clock
• In a master clock, clock definition point is the origin of the master clock
• In a generated clock, clock definition point is the master clock
• "The start point of a clock path is always the master clock definition point"
• Advantage of generating a clock : " Source latency is not automatically included" b. Methods to create a generated clock using : -- "-edges" -- "create_generated_clock" -- "-invert" c. Clock latency for Generated Clocks
• A source latency specified on a generated clock specifies the latency from the defition of the master clock to the definition of the generated clock.
• Total clock latency (Generated Clock) = Source latency (Master + Generated clock ) + Network Latency (Generated Clock)

d. Typical Clock generation scenario

• Assume an Oscillator which is external to the chip produces a low freq clock which is used as a reference clock by the on-chip PLL to generate a high-frequency low-jitter clock.
• This clock is then fed to a clock divider that generates the required clocks for the ASIC
• A master clock is defined for the referenc clock at the input pin where it enters the chip and a seocond master clock is defined at the output of the PLL.
• PLL output clock has no phase relationship with the reference clock. Hence, output clock shouldn't be a generated clock of the reference clock.
• All clocks generated by the clock divider logic are specified as generated clocks of the master clock at the PLL out-put.

Constraining the Input paths

which is internal to the design. The data is connected through the input port INP1. 3. The clock definition for CLKA specifies the clock period, which is the total amount of time available between the two flip-flops UFF0 and UFF1. 4. The time taken by the external logic is Tclk2q, the CK to Q delay of the launch flip-flop UFF0, plus Tc1, the delay through the external combinational logic. Thus, the delay specification on an input pin INP1 defines an external delay of Tclk2q plus Tc1.

• set Tclk2q 0.9 set Tc1 0.6 set_input_delay -clock CLKA -max [expr Tclk2q + Tc1] [get_ports INP1]
• The constraint specifies that the external delay on input INP1 is 1.5ns and this is with respect to the clock CLKA. Assuming the clock period for CLKA is 2ns, then the logic for INP1 pin has only 500ps (= 2ns - 1.5ns) available for propagating internally in the design. This input delay specification maps into the input constraint that Tc2 plus Tsetup of UFF1 must be less than 500ps for the flip-flop UFF1 to reliably capture the data launched by flip-flop UFF0. Note that the external delay above is specified as a max quantity

Constraining the output paths

• Output delay is specified related to the capture clock
• Total delay of the external logic is Tsetup + Tcq

Output must be ready at the output port before the shaded region starts and should be stable all the way through the shaded region

Timing path groups

In STA, the paths are timed based upon valid start points and valid endpoints. Valid start points : Input ports, clock pins of synchronous design Valid end points : Output ports and data input pins of synchronous devices

i. from an input port to an output port. ii. from an input port to an input of a flip-flop or a memory. iii. from the clock pin of a flip-flop or a memory to an input of flipflop or a memory. iv. from the clock pin of a flip-flop to an output port.

Timing paths are sorted into path groups by the clock associated with the endpoint of the path.

STA and reporting are done separately on each path group.

Other important constraints to accurately model the environment of a design

Design rule checks.

These checks ensures that all ports and pins in the design meet the specified limits for transition time (slew) and capacitance.

Other design rule checks are set_max_fanout and set_max_area. These checks usually apply for synthesis not for STA.

Virtual Clocks

Refining the timing analysis.

i. Four common commands that are used to constraint the analysis space are as follows.

a. set_case_analysis

b. set_disable_timing

c. set_false_path

d. set_multicycle_path

Specifying inactive signals

ii. This helps in reducing the analysis space in addition to not reporting any paths that are irrelevant. iii. Such constant signals are specified by using the set_case_analysis specification. iv. When a design can run on multiple clock, and the selection of appropriate clock is controlled by multiplexers. To make STA analysis easier and reduce CPU run time, it is beneficial to do STA for each clock selection separately.

Breaking Timing arcs

ii. It is done using set_disable_timing SDC command. iii. Another example of similar usage is to disable the minimum clock pulse width check of a fli-flop.

Point to point specification

ii. set_min_delay

Path segmentation

ii. A timing path has a start point and an end point. iii. Additional startpoints and endpoints on a timing path can be created using the set_input_delay and set_output_delay specifications. iv. set_input_delay which defines a startpoint, is typically specified on an output of a cell. v. set_output_delay which defines a new endpoint is typically specified on an input of a cell.

VLSI Physical Design

Monday, october 5, 2015, case analysis and mode analysis.

Hi, Can you add more information about how can you implement this with PrimeTime? So I understand that I have to use some input ports to configure them with mode that I want to run, but in this case those ports are not analysed?

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synthesis: Synopsys DC

DC (Design Compiler):  This is the synthesis tool from Synopsys, which takes RTL as input and generates a synthesized netlist.

For running synthesis in Design Compiler: ------------------------------------------------------------------- In synthesis, clk and scan_enable are set as ideal network, so they don't get buffered (they get buffered in PnR). Reset and all other pins are buffered as needed to meet DRC. This reset tree built in DC is again rebuilt in PnR during placement to make sure it meets recovery/removal checks. steps in DC synthesis are as follows:

1. RTL opt: HDL-Compiler compiles HDL (performs translation and arch opt of design). DC translates HDL desc to components extracted from GTECH(generic tech) and DW(Design Ware) lib called as RTL opt. GTECH consists of basic logic gates and flops, while DW contains complex cells as adder, comparators, etc. these are tech independent. 2. Logic opt: DC then does logic opt. first, it does structuring which adds intermediate variables and logic structures to GTECH netlist. then it does flattening which converts combo logic paths into 2 level SOP rep. At this stage, all intermediate variables and it's associated logic structure are removed. 3. Gate opt: it optimizes and maps GTECH design to specific tech lib (known as target lib). It's constraints driven. It does delay opt, design rule fixing and area opt. Power Compiler used if static/dynamic power opt done. 4. Add DFT: Next Test synthesis is done using DFT Compiler, which integrates test logic into design. 5. Place and Route (PnR): PnR is done next, from which delays can be back annotated to design. DC can then resynthesize to generate better netlist.

Operating condition for any chip is defined via 3 conditions: Process (P), Voltage (V) and Temperature (T). Since these 3 uniquely determine the speed of transistor, we choose a particular PVT corner for running Synthesis. Usually we define 3 PVT corners (below ex is for a design in 250nm). The term max, min, etc refers to delay, so max corner means corner with maximum gate delay, i.e slowest corner.

NOM: P=TYP, V=1.8V, T=25C (TYP) => This is the typical or nominal corner where chip is supposed to run at nominal speed. Here PVT is specified as 1.8V, room temperature and nominal process. MAX: P=WEAK, V=1.65V, T=150C (WC) => This is the worst case corner, where chip is supposed to run at the slowest speed. Here PVT is specified as 1.65V, high temperature and weak (slow) process. MAX implies this PVT gives you maximum delay (i.e slowest speed). You will note that voltage is -10% below typ. This is generally a safe voltage to choose as voltage is not supposed to fluctuate by more than +/- 10% even in worst case scenarios (as voltages are usually controlled by PMU, which hold voltage levels very tight. Most of the voltage fluctuations happen due to IR drop on and off chip). MIN: P=STRONG, V=1.95V, T=-40C (BC) => This is the best case corner, where chip is supposed to run at the slowest speed. Here PVT is specified as 1.95V, low temperature and strong (fast) process. MIN implies this PVT gives you minimum delay (i.e fastest speed). Voltage here is usually +10% above typ

Since we want our design to be able to run in worst possible scenario, we choose WC (MAX) corner to synthesize our design. Then, our design is guaranteed to work across all OP conditions.

dc_shell-t -2010.03-SP5 => brings up DC shell. dc_shell is shell mode (dc own shell), while dc_shell-t is tcl mode (dc shell which can accept tcl cmd too). dc_shell-xg-t is XG mode, which uses opt mem mgmt to reduce run time. dc_shell-t -2010.03-SP5 -f ./tcl/top.tcl | tee logs/my.log => runs with cmds in top.tcl and keeps all info printing on screen to my.log dc_shell-t -2010.03-SP5 -t topo -f ./tcl/top.tcl => To bring dc-shell-t in topo mode. This requires MilkyWay (MW) db. See section in synopsys ICC (PnR_ICC.txt)

When we run in DC shell above, it's a text based shell. We can also have GUI. Design Vision is GUI for synopsys synthesis env. symbol lib is needed to generate design schematic. To start gui, either run "dc_shell -gui", or from within dc_shell, run "gui_start". DC family: 1. DC Expert (compile cmd used). 2. DC Ultra(compile cmd used). Help in DC: type "help" or "cmd_name -help" or "man cmd_name" setup file for DC:

We have a setup file for DC that DC reads before invoking DC shell. This file is .synopsys_dc.setup and is usually put in the dir from where DC is invoked. This file has search paths, lib path and other variables setup. Note this file can be copied from some other project by using: cp dir1/.synopsys_dc.setup to dir2/. .synopsys_dc.setup => This file can have all common settings that you want to apply to your design. It can source other tcl files or set parameters for DC. At a minimum, it needs to set search_path, target_library and link library.

set search_path "$search_path /db/pdk/tech45nm/.../synopsys/bin" => adds this path to default path to search for design and lib files set target_library TECH_W_125_1.6_STDCELLS.db => this lib, which should be present in search path above, is used during compile to gen gate level netlist. worst case (wc) lib chosen, as we try to meet setup for wc corner. taget_library is used by opt engine to map design to, so it should have all stdcells that are required for mapping. set link_library {* TECH_W_125_1.6_STDCELL.db }  => link_library (or link_path) is a superset of target_library. resolves references. First looks in DC mem (* means DC mem which has design files), then in specified .db (same as target_library files) for matching lib cell name and then any other libraries which are not target for opt, but may be present in design (as Macro, RAM cells). In DC, we don't need Clock cells (i.e buffers, inverters specifically made for clk tree), so in many companies, clk cells are all put in a separate library, so that we don't have to load unnecessary library cells during synthesis.

link library are synopsys .db files (liberty files in db format) and our design are *.ddc/*.db files. We put *, so that on top of liberty files, DC searches in all the designs already loaded in mem (i.e for module named A in top.db, it searches in A.db, before it looks for A in .lib files). If we omit *, it will cause link failures, as hier designs have modules, which it won't be able to find any more. NOTE: Most lib/db files have file name same as library name within that file. i.e "TECH_W_125_1.6_STDCELL.db" is defined as library within the file "/db/tech45/.../TECH_W_125_1.6_STDCELL.db". "target_library" and "link_library" refers to file names ?? FIXME ??. Also, we can also provide the full path name of the file so that search_path is not needed for finding target and link libraries.

ex: set target_library "/db/tech/.../TECH_W_125_1.6_STDCELLS.db"

NOTE: In PT, we use PnR netlist which has Clk cells, so we add db for clk cells also when running PT. NOTE: if we have hard IP blocks, then db files for those blocks should be included in link_library, and paths for those should be in search path. That way, we don't have to provide RTL code for that IP. DC sees that cell name in the db file present in any of target and link lib, and on finding them there, it doesn't complain about missing cell.

Ex: sram2048x32 (sram cell). We instantiate "sram2048x32" in RTL file digtop.v and also have a rtl file (sram2048x32.v) for this module. Then, when running DC, we don't analyze and synthesize rtl file "sram2048x32.v" (i.e this verilog file is not provided in list of RTL files). DC looks at module name "sram2048x32" and tries to find this cell in link_library. It finds this "cell (sram2048x32)" stmt in "sram2048x32_W_125_1.65.db" file, which is present in link library.At this point, tool is happy, otherwise it would search for "sram2048x32" module in any of the other rtl files. This is similar to what happens if we instantiate a latch (LATCH10) directly in RTL, then DC looks for that cell in target_library and link_library. It finds them in "TECH_W_125_1.6_STDCELL.db" file as "cell (LATCH01)" and hence doesn't complain, otherwise it would look for LATCH10 module in any of the RTL files being analyzed, and on not finding the module, it would complain.

#symbol_library => defines symbols for schematic viewing of design. #synthetic_library => to specify any specially licensed DW lib. Std. DW lib are included by default. NOTE: only .db library can be read in DC. If we have library in .lib format, then we need to convert it to .db using cmds below and then use those. #read_lib /db/.../rom_W_150_1.65.lib => This file will be read and stored as *.db file in mem. list_libs will now show this lib too as .db write_lib rom_W_150_1.65.db -f db -o /db/.../rom_W_150_1.65.db => optional. This saves file in path specified so that next time .db file are directly available to be read by DC (saves run time??). #if we want to do max/min timing using max/min lib, then we need to do as explained in create_views of PnR_ICC.txt. #list_libs => lists which lib are used as max lib (denoted by M), and which for min lib (denoted by m). We should see all db library, and in which db file they are. dw_foundation.sldb, gtech and standard.sldb lib are also shown with their paths. #report_lib => reports contents of lib as units, op cond, WLM and cells. Use this to see library units for cap, resistance, etc present in the library. #which abc.db => shows absoulte path for this .db file that is being used currently.

Difference between target library and link library, and why do we need both?

Target lib are lib that you target for mapping your RTL to gates. These are std cells which are provided as target. DC chooses from amongst this set, a subset of cells to optimize the final mapped design. On the other hand, link lib  resolves references in the design by linking the instances, references in the RTL with the link libraries . So, in link lib, we provide target lib plus any IP as memory, PLL, analog blocks etc, which are needed strictly for linking. These IP lib are not needed for optimizing but just for linking (as they contain just 1 lib that we force to link). So, link lib contain target lib + extra macro libs.

So, the question is why do we need both, when we are specifying same libraries in target and link? Reason might be that it's easier for the tool to have different lib settings for "OPTIMIZATION-MAPPING" & "LINKING".That way it knows what to pick for optimizing and mapping, and what to use for strick one to one mapping.

Below is a sample DC script that can be used to run synthesis. We start with the top most file known as top.tcl.

top.tcl: this is the main tcl file that is sourced by the DC tool from cmd line. All DC cmds are in this file, and DC starts running cmds from this file until it reaches end of this file. These are the various sections of this script in tcl: 1. Read all RTL files, and link the library of cells/IP. #source some other files #NOTE: for source to work, file path has to start with ./ so that it looks for that file in unix dir, else DC will look for that file in it's memory which doesn't have that file, so it will error out. source ./setup.tcl => In this file set some variables, i.e "set RTL_DIR /db/dir" "set DIG_TOP_LEVEL  digtop" or any other settings #this is to suppress warnings during analyze/elaborate suppress_message {"LINT-1" "LINT-2" "LINT-10" "LINT-33" "LINT-8" "LINT-45" "VER-130" } #read verilog/vhdl/systemVerilog files. DC can also rd in .ddc & .db (snps internal format, .ddc recommended), equation (snps equation format), pla (berkeley espresso PLA format) and st (snps state table format). 2 ways: 1. Analyze and elaborate => analyzes (compiles, checks for erros and creates an intermediate format) and elaborates HDL design, and stores it in snps lib format file for reuse. All subdesigns below the current design are analyzed, and then elaboration performed only at top level. During elaboration, RTL compiler builds data structures, infers registers in design, performs high level HDL optimization, and checks semantics. It translates the design into a technology-independent design (GTECH) from the intermediate files produced during analysis. It replaces  HDL arithmetic operators in the code with DesignWare components and automatically executes the link command, which resolves design references After elaboration, RTL compiler has internally created data structure for the whole design on which it can perform operations. cmds: analyze -format verilog|vhdl [list a.v b.v] => on doing analyze, WORK dir created which has .pvl, .syn and .mr file for each verilog module. Runs PRESTO HDL Compiler for RTL files, and then loads all .lib files. analyze -autoread [list a.v b.v c.vhd] => to auto analyze mix of verilog and vhdl files elaborate <top level verilog module name, VHDL entity or VHDL configuration> => ex: elaborate digtop => loads gtech.db and standard.sldb from synopsys lib, and link library *_CORE.db and *_CTS.db from user defined lib, and then builds all modules. It infers memory devices (flip flops, and appends _reg to the net name storing the value i.e net <= value), analyzes case stmt (full case[all possible branches specified so combinatorial logic synthesized, else latch synthesized for non full case], parallel case[case items don't overlap, so mux synthesized, else for non-parallel case, priority checking logic synthesized]) 2. read_file -f <verilog|vhdl|db/edif> filename => we can also use read_verilog, read_vhdl, read_db and read_edif, instead of specifying file type in read_file. this can be used to read in gate level netlists also that are mapped to a specific tech. This also performs analysis and elaboration on HDL designs written in RTL format, but it elaborates every design read, which is unnecessary. Only top level design needs to be elaborated. read_file is useful if I want to reuse previously synthesized logic in my design. #We use 1st way shown above: do analyze and elaborate and then set current_design analyze -format verilog [list "/db/.../global.v" "/db/.../utils.v" ... "/db/.../digtop.v" ] elaborate      digtop => since digtop is top level module current_design digtop => current design always needs to be set to top level #for design references during linking, DC uses the system variables link_library and search_path along with the design attribute local_link_library to resolve design references. link library has library cells (from .lib) as well as subdesigns(modules inside top level module) that the link cmd uses. link => resolves references. and connects the located references to the design. #To see the reference names, use the following command: #get_references AN* => returns coll of instances that refer to AN2, AN3 etc. ex o/p = {U2 U3 U4} dc_shell> report_cell [get_references AN*]  => shows references for AN2, AN3, etc for cells and the library to which it's linked. At this stage, lib is GTECH and all references are from this GTECH library. so, use * to see all references. dc_shell> report_cell [get_references *]  => this shows all ref for cells present in top level design. If there is any logic stmt (i.e assign = A&B; etc) in top level, then it gets mapped to GTECH cells as GTECH_OR, GTECH_AND, etc and gets reported too. Cell                      Reference       Library             Area  Attributes -------------------------------------------------------------------------------- B_0                       GTECH_BUF       gtech           0.000000  c, u C29                       *SELECT_OP_2.1_2.1_1            0.000000  s, u C54                       GTECH_AND2      gtech           0.000000  u ccd_top                   ccd_top                         4.000000  b, h, n, u revid_tieoff              TO010           PML30_W_150_1.65_CORE.db  1.750000 -------------------------------------------------------------------------------- Total 42 cells                                            172.500000 2. specify constraints: env constraints (PVT), design constraints(area/max_fanout) & timing constraints(clks/false_paths) constraints: IMP: all constraints are specified in sdc format. see sdc.txt for details of constraints. 2 set of constraints: 1. env_constraints = i/p driver, o/p load, i/p delay, o/p delay, dont_touch, dont_use 2. design constraints:    A. design rule const: max_fanout, max_transition, max_cap    B. optimization constraints:       I. timing constraints = clks, generated clk, false path, multicycle paths, (if false_paths refer to gate level netlist, then initial mapped netlist needed)       II. power contraints = max_power       III. area constraints = max_area A. environment constraints: as op cond (PVT), load (both i/p and o/p), drive (only on i/p), fanout(only on o/p) and WLM. #set_operating_conditions: see in PT OCV section for details of this cmd. set_operating_conditions -max W_150_1.65 -library STD_W_150_1.65_CELL.db (Instead of set_operating_conditions we can also use "set_max_library STD_W_150_1.65_CELL.db) => Here, we are using our max delay library for both setup/hold runs. We can check this by looking in reports/digtop.min_timing.rpt. FIXME # LBC8/PML30 lib uses 1.8V PCH_D_1 and NCH_D_1 (Lmin=0.6um drawn), cell height=13.6um, 8routing tracks available, with 3,4,5 Layer for metal routing. 1X inv has i/p cap of 6ff. Power is about 0.1uW/gate/Mhz (CV^2f= 6ff*1.8^2*10^6/MHz = 0.15uW/MHz for inx1) FIXME #WLM: wire load model: used only when design is not in physical mode. set auto_wire_load_selection true #set_wire_load_model "6K_3LM" => sets wire load model on current design to something other than the default one set in .lib file. Usually for larger designs, we set WLM manually, since the default WLM may be smaller designs, and so too optimistic. # Setting enclosed wire load mode. mode may be top|enclosed|segmented set_wire_load_mode enclosed => Here, multiple WLM are specified for various sub-modules, so for a net which traverses multiple sub-modules, WLM of that higher level module used which completely encompasses the net. When mode is "top", then WLM of top level module used for all nets in design. Since WLM is defined only for top level design above, WLM for lower level sub-modules are chosen as default when mode=enclosed or segmented. report_design => see in PT OCV section for details of this cmd. shows all libs used, op cond used (PVT from WLM used, etc. ##### DC TOPO flow starts: see in PnR_ICC.txt for details. comment out the WLM portion above for DC-TOPO. #create MW lib if one doesn't exist already. From next time, we can just open created desgin lib. create_mw_lib -technology /db/DAYSTAR/design1p0/HDL/Milkyway/gs40.6lm.tf \     -mw_reference_library "/db/DAYSTAR/design1p0/HDL/Milkyway/pml48MwRefLibs/CORE /db/DAYSTAR/design1p0/HDL/Milkyway/pml48ChamMwRefLibs/CORE" \     -open my_mw_design_lib open_mw_lib my_mw_design_lib set_check_library_options -cell_area -cell_footprint check_library #set TLU+ files instead of WLM. set_tlu_plus_files \     -max_tluplus /db/DAYSTAR/design1p0/HDL/Milkyway/tlu+/gs40.6lm.maxc_maxvia.wb2tcr.metalfill.spb.nlr.tlup \     -min_tluplus /db/DAYSTAR/design1p0/HDL/Milkyway/tlu+/gs40.6lm.minc_minvia.wb2tcr.metalfill.spb.nlr.tlup \     -tech2itf    /db/DAYSTAR/design1p0/HDL/Milkyway/mapping.file check_tlu_plus_files ######DC-TOPO flow ends #naming convention for lib objects varies b/w vendors, but for SNPS, it's "[file:]library/cell/[Pin]" (file and pin are optional). Ex: to access AND2 cell: set_dont_touch /usr/designs/Count_16.ddc:Count_16/U1/U5. #i/p drives set_driving_cell -lib_cell IV110 [all_inputs] => all i/p ports driven by IV110 #set_drive/set_input_transition #i/p and o/p loads. (i/p load needed when there is extra load due to wire or extra fanout not captured in input gate cap) set output_load    [get_attribute [get_lib_pins {"PML30_W_150_1.65_CORE.db/IV110/A"}] capacitance] set output_load_4x [expr 4 * $output_load] set_load $output_load_4x [all_outputs] => setting FO=4 load on all o/p pins. (set_load can be used on any net, port) #NOTE: If we set o/p load to be very high (i.e 1pf), then all o/p ports will get driven by largest INV/BUF as any other logic gates don't have that drive capability to drive such a high load. So, on such ports Isolation buffers may not be needed in PnR flow, as buffers are already there from synthesized netlist (if we do put buffers in PnR flow, then we will have 2 buffers back to back for each port, resulting in area wastage) global constraints: ----------- #set_dont_use set_dont_use PML30_W_150_1.65_CORE.db/LA* => don't use latches from lib set_dont_use PML30_W_150_1.65_CORE.db/DTB* => don't use D-flops with preseet and clr #set_dont_touch => prevents specified object (net,instance,etc) from being modified duing optimization. Ex: set_dont_touch [get_cells {TWA/FF1}] => prevents the specified instance from being modified Ex: set_dont_touch [get_nets -of_objects [get_cells {TWA/FF1}]] => i/o preserved for that cell. set_dont_touch scan_inp_iso => prevents module instance from being modified. B. design constraints: design rule and optimization constraints. For initial synthesis, we only provide env_constraint and not design constraints (as we just need gate mapping for RTL to write our false path file) ---------------- 1. design rule constraints: usually provided in .lib. typical constraints are set_max_transition, set_max_fanout, set_max_capacitance. These cosntraints are associated with pins of the cells in lib, but eventually end up constraining nets of design. DC prioritizes these over opt constraints, and tries not to violate them. clk nets and constant nets have design rule fixing disabled by default, scan nets do not. i/p ports of design have max_cap figured out by cells driving i/p port (using set_driving_cell in sdc file), while o/p ports have max_cap figured out by cells driving o/p port (size of cells driving o/p port is picked up based on load on o/p port (using set_load in sdc file). o/p port max_cap is seldom violated because DC picks up right size gate to drive the o/p load. However, i/p port max_cap may be violated if we didn't pick right size buffer to drive heavily loaded pins (as i/p clk pin, reset pin, etc). NOTE: For bidir pins, it's treated as both i/p and o/p pin, so it has a driver as well as a load. That makes it harder to meet max_cap requirement of external driver if external driving buffer is not chosen properly, while a large cap load is placed on the pin (It may easily meet internal driver max_cap requirement as the tool can size the internal driver appr). It may also fail max_transition, as if max_cap gets violated, then depending on how bad it failed, the external driving buffer may need to extrapolate timing for excess cap load, resulting in max_transition violation. To avoid this, choose appr external driver for bidir pin. ###design rule const:  We don't set any DRC as all these are picked as per .lib 2. opt constraints: opt const for timing provided later during incremental compile. set_max_area       0 ---- #set_fix_multiple_port_nets: sets "fix_multiple_port_nets" attr on the design specified. #This attribute controls whether compile inserts extra logic into the design to ensure that there are no feedthroughs, or that there are no two output ports connected to the same net at any level of hierarchy. The default is not to add any extra logic into the design to fix such cases. Certain three-state nets cannot be buffered, because this changes the logic functionality of the design. #-all: insert buffers for o/p directly connected to i/p(-feedthrough), inserts buffers if a driver drives multiple output ports(-outputs) and duplicate logic constants so that constants drive only 1 o/p port # -buffer_constants: buffers logic constants instead of duplicating them. set_fix_multiple_port_nets -all -buffer_constants [get_designs *] #set_isolate_ports: Specifies the ports that are to be isolated from internal fanouts of their driver nets. #-driver BU140 => BU140 or other size buffer used to isolate. By using -force, we force the driver to be the size specified (i.e BU140 only, no other size allowed), and also force isolation to be done on all ports specified, even if they don't need isolation. #we don't put isolation cells during synthesis, as we do it during PnR. #set_isolate_ports -driver BU140 -force [all_inputs] #set_isolate_ports -driver BU140 -force [all_outputs] ---------------------------- # Uniquify after applying constraints current_design $DIG_TOP_LEVEL link uniquify => NOT necessary, since this step is done as part of compile. Removes multiple-instantiated hierarchy in the current design by creating a unique design for each cell instance. So, if you do get_designs * => it now shows multiple instances of clk_mux with clk_mux_1, clk_mux_2, etc. So, each of these clk_mux_* have the same rtl, but they can now be optimized separately. #Provide physical info (area, placement, keepout, routing tracks, etc) abt floorplan if in DC-TOPO mode. 3 ways: 1. write_def within ICC, and then import it into DC by using extract_physical_constraints cmd. ex: extract_physical_constraints {design1.def ... design2.def} 2. write_floorplan cmd in ICC which generates a tcl script, and then read that file using read_floorplan. ex: read_floorplan -echo criTop.all.fp.tcl => this tcl file is generated by write_floorplan cmd in ICC, and used here in DC. 3. Manually provide physical info. Put these constraints(die area, port locations, macro, keepout, etc) in a tcl file and source it. these constraints are the one that we use in ICC to force the tool to generate desired placement. ##### opt const (speed): clk related info here (set_input_delay, set_output_delay provided during incremental compile) create_clock -name "spi_clk" -period 50 -waveform     { 2 27 } [get_ports spi_clk] => 20M clk, rising edge at 2ns and falling edge at 27ns. set_clock_uncertainty 0.5 spi_slk => adds 0.5 units skew to clk to model skew during CTS in PnR. # generated Clock: NOTE: this cmd sometimes requires the presence of synthesized netlist, as the target pin list may be o/p of flops, etc so, we use this cmd after the initial compile. create_generated_clock -name "reg_clk" -divide_by 1  -source [get_ports clock_12m] [get_pins clk_rst_gen/pin1] => apply waveform on pin "clk_rst_gen/pin1" #optional ideal attr => not needed for DC. clk nets are ideal nets by default. #set_ideal_network -no_propagate {clk1 clk2} => marks a set of ports or pins  in  the  current  design  as sources  of an ideal network. compile command treats all nets, cells, and pins on the transitive fanout of these objects  as ideal (i.e no delay). transition time of the driver is set to 0ns. Propagation  traverses through combinational cells but stops at sequential cells. In  addition  to disabling timing updates and timing optimizations, all cells and nets in the ideal network have the dont_touch attribute  set. "-no_propagate" indicates that the ideal network is not propagated through logic gates (i.e logic gates encountered are treated as non-ideal with non-zero delay). By default, ideal property is propagated thru gates. NOTE: during report_timing, we see transition time on these ports/pins as 0ns, resulting in no "max_transition_time" violations.   #set_ideal_latency 2 clk1 #set_dont_touch_network [get_clocks *] #set_propagated_clock [all_clocks] #set ideal n/w for scan_enable, so that they don't get buffered in DC, will be buffered in PnR #set_ideal_network -no_propagate {POR_N I_CLK_GEN/POR_N_SYNCED} => NOT needed. POR_N port only goes to 2-3 flops as it gets synced first, then the synced version goes to all flops. We don't set any of these ports to ideal as that will prevent tool from putting buffers on these paths. These paths result in max_cap, max_trnasition viol (not timing viol as async paths aren't checked for timing in DC), so DC will buffer these to prevent those viol. If we do not want to buffer the reset tree in DC, we can use this cmd to prevent buffering in DC, and then buffer it during PnR. However, the sdc file exported to PnR tool should have this cmd removed so that PnR tool can buffer it. Also, no false_path should be set starting from "POR_N_SYNCED" pin as it's a real path. We can set false path starting from "POR_N", but even that's not required #set_ideal_network -no_propagate I_CLK_GEN/SCANRESET => NOT needed as it feeds in same reset tree. #set_ideal_network -no_propagate scan_en => this done during scan stitching. Here, scan_en not set to ideal is OK, as this net is not connected to any flop (it's a floating net at this stage, and scan_enable/scan_data pin of all flops is tied to 0 or 1). So, no opt takes place on this net. Later during dft scan stitching step, scan_en gets tied to pin of all flops, that is where we set it to ideal, so that it doesn't get buffered. # Specify clock gating style => Sets  the  clock-gating  style  for the clock-gate insertion and replacement #-sequential_cell none | latch => 2 styles. A. latch free ( no latch, just and/or gate, specify none). B. latch based (latch followed by and/or, default) #-positive_edge_logic {cell list | integrated} => for gating +ve FF inferred from RTL. For latch based, cell list must be AND/NAND (can also specify latch in cell list). For latch-free, cell list must be OR/NOR. integrated => Uses a single special integrated clk gating cell from lib instead  of  the  clock-gating circuitry (i.e latch followed by and/nand). With integrated option, we can say whether enable signal is active low and if clk is inverted within the integrated cell. when using integrated clk gaing cells, setup/hold are specified in lib, so separate -setup/-hold options are not required. Tool identifies clk gating cells in lib by looking for clock_gating_integrated_cell. For CGP, it's "latch_posedge", and for CGPT, it's "latch_posedge_precontrol". For CGN, it's "latch_negedge", and for CGNT, it's "latch_negedge_precontrol". #-negative_edge_logic {cell list} => same as above except that for latch based, cell list must be OR/NOR (can also specify latch in cell list). For latch-free, cell list must be AND/NAND. #-control_point none | before | after => Final_En = (En | Scan_en). Before or after determines whether to put the OR gate before or after the latch. The  tool  creates  a new  input  port to provide the test signal.  The control points must be hooked up to the design level test_mode  or  scan_enable port using the insert_dft command. #-control_signal scan_enable | test_mode => Specifies  the test control signal.  If an input port is created and the argument is  scan_enable, the name of the port is determined by the test_scan_enable_port_naming_style variable, while for test_mode, the name of the port is determined  by  the  test_mode_port_naming_style  variable. test_mode signal is the one that is asserted throughout scan testing, while scan_enable signal is asserted only during scan shifting (All FFs have scan_enable  the select line of their internal mux). Ususally it's set to scan_enable. set_clock_gating_style -control_point       before \                        -control_signal      scan_enable \                        -positive_edge_logic integrated \                        -negative_edge_logic integrated

3. synthesize/compile design (initial stage):

#2 types of compile strategy: A. top-down: top level design and all it's subdesigns are compiled together. Takes care of interblock dependencies, but not practical for large designs, since all designs must reside in memory at same time. B. Bottom-up: individual subdesigns are constrained and compiled separately. After successful compilation, the designs are assigned the dont_touch attribute to prevent further changes to them during subsequent compile phases. Then the compiled subdesigns are assembled to compose the designs of the next higher level of the hierarchy, and those designs are compiled iteratively until the top level design is synthesized. # Initial Compile #-scan: replaces normal flops with scan version. connects scan pins to tiehi or tielo (doesn't do actual stitching of scan pins here) #DC uses design rule cost and opt cost to determine cost fn. use -no_design_rule to disable design rule cost (max_tran, max_fo, etc) and -only_design_rule to disable opt rule cost (delay, power, area, etc). hold violations are fixed only if set_fix_hold and set_min_delay is specified for design. otherwise, only max_delay (not min_delay) is part of cost fn. We can reorder priority of design/opt constraints to get new cost fn by using set_cost_priority. #-gate_clock: enables clk gating opt as per options set by set_clock_gating_style cmd. clk gates inserted are wrapped inside a clk_gating module which has CG* cell. #-no_autoungroup: all user hier are preserved (i.e ungrouping is disabled). Required, else ungrouping removes hier boundaries and flattens the netlist to optimize across modules. Without this, some hierarchies were being flattened to implement clock gating compile_ultra -scan -no_design_rule -gate_clock -no_autoungroup #check_design => checks synthesized design for consistency. #check_timing #report_clocks # reports after compile set rptfilename [format "%s%s" $mspd_rpt_path $DIG_TOP_LEVEL.initial_area.rpt ] #redirect => Redirects the output of a command to a file. -append appends o/p to target redirect $rptfilename {echo "digtop compile.tcl run : [date]"} redirect -append $rptfilename {report_area -hier} => reports total area for combo & non-combo logic. also reports total no of cells at top level of design (in module digtop, counting 1 for each sub-module and 1 for each stdcell), no. of I/O ports and no of nets (total no. of wire in digtop). -hier reports it for all hier modules. area is taken from area in .lib file (RAM/ROM IP usually have incorrect area, as they aren' scaled in terms of NAND2 equiv size) redirect -append $rptfilename {report_reference -hier} => reports all references in current instance (if current inst set) or current design (default). It reports all instances in top level module of current design, which has subdesigns(as other modules), as well as some std cells connecting these modules together). -hierarchy option goes thru the hier of sub modules and reports all leaf cell refrences. #NOTE: we can use above 2 cmds for any netlist to report total number of gates. For ex, to find out total gates in routed netlist, do: read_verilog ./DIGTOP_routed.v current_design DIG_TOP   report_area -hierarchy #NOTE: no constraints of any sort (i/p, o/p delay, false paths, etc) are applied above, as we just want to get a verilog netlist mapped from RTL. Even clk wasn't required to be declared, as we aren't running any timing on this netlist. # Initial Compile ----------------------------------------------------------------------------- # Clean up # removes unconnected ports from a list of cells or instances, perform link and uniquify before this command # -blast_buses -> if a bus has an unconnected port, the bus is removed. #find => Finds a design or library object. -hierarrchy means at any hierarchy of design. Ex: remove_unconnected_ports -blast_buses find( -hierarchy cell, "*") remove_unconnected_ports -blast_buses [find -hierarchy cell *] #to ensure name consisitency b/w netlist and other layout tools => define_name_rules and change_names cmd used to convert names. define_name_rules defines our own rules, and change_names applies the change to the netlist for the particular rule. There are already std rules for verilog/vhdl. Sometimes, we keep these cmds in .synopsys_dc.setup, so that they are always applied. # change_names of ports, cells, and nets in a design. -hierarchy Specifies that all names in the design hierarchy are to be modified. (report_name_rules shows rules_names are sverilog,verilog,verilog_1995 and vhdl). This cmd should always be applied before writing netlist, as naming in the design database file is not Verilog or VHDL compliant. #report_names => shows effects of change_names w/o making the changes. change_names -rules verilog -hierarchy => std verilog rule applied to all hier of netlist. #define_name_rules <rule_name> -map { {{string_to_be_replaced, new_replaced_string}} } -type cell define_name_rules     reduce_underscores   -map { {{"_$", ""}, {"^_", ""}, {"__", "_"}} } => names a rule which removes trailing underscore, starting underscore and replaces double underscore with a single underscore. change_names -rules   reduce_underscores   -hierarchy => rule applied define_name_rules    reduce_case_sensitive   -case_insensitive change_names -rules  reduce_case_sensitive   -hierarchy -verbose #not sure ??? apply_mspd_name_rules_noam ------------------------------------------------------------------------------ #DC doesn't automatically saves designs loaded in memory. So, save design before exiting. #save design using write: saves in .ddc, .v, .vhdl format #save design using write_milkyway: writes to a milkyway database. write -format ddc     -hierarchy -output ./netlist/${DIG_TOP_LEVEL}_initial.ddc \ => preferred, .ddc is internal database format write -format verilog -hierarchy -output ./netlist/${DIG_TOP_LEVEL}_initial.v => verilog format (also supports systemverilog (svim) and VHDL format o/p.

4. synthesize/compile design (incremental stage):

# Apply constraints for func mode, when scan exists source tcl/case_analysis.tcl => specify which scan related pins need to be tied for func mode. It has these stmt: #set_case_analysis => Sets  constant  or transitional values to a list of pins or ports and prop thru logic for use by the timing engine. The specified constants or transitional values are valid only during timing analysis and do not alter the  netlist. set_case_analysis 0 scan_mode_in => we force Scan_mode to 0, as we want to see timing paths b/w diff clocks. false paths take care of bogus paths b/w clock domains. forcing it to 1 will cause all clocks to be the same clock (i.e scan_clk), so, we won't be able to see inter clock paths. If we don't force scan_mode at all, then both scan_mode=0 and scan_mode=1 timing analysis is run. #set_case_analysis 0 scan_en_in => we should NOT force this to 0, as we want timing for scan shift paths also. # all constraints for all i/o pins here (opt constraints) source tcl/constraints.tcl => Put all i/p o/p delays here #we may want to leave setting i/p delays, so that in PT we can see them as "endpoints not constrained" warning. This helps us to see which all are pins which are going thru meta flop. set_input_delay 0.2 -clock clk1 [remove_from_collection [all_inputs] [get_port {clk1}]] => sets 0.2 unit delay on all i/p pins (except clk1 port) relative to clk1. sET_output_delay 0.4 -clock clk1 [remove_from_collection [all_outputs] [get_port {spi_miso}]] => 0.4 delay for all o/p ports except spi_miso #create generated clocks here since it may refer to pins of flops, etc which may only be present in synthesized netlist source tcl/gen_clocks.tcl #all clks treated as div by 4 clk, since very large divided clks will cause longer run time. #we don't have long delay paths, so even if we define very fast clks as div by 4 clk, we should not see any failing paths for setup. It will screw up hold time calc, as PT treats hold time based on no of clk edges that lies in b/w one setup path. # Div 4 clk create_generated_clock -name "clk_1600k"        -divide_by 4  -source [get_ports clkosc] [get_pins Iclk_rst_gen/clk_count_reg_1/Q] create_generated_clock -name "clk_100k"         -divide_by 4  -source [get_ports clkosc] [get_pins Iclk_rst_gen/clk_count_reg_5/Q] #ram latch clock (since clk signal, generated as a pulse, may be o/p of flop). We can do div by 1 also. create_generated_clock -name "clk_latch_reg"    -divide_by 2  -source [get_ports clkosc] [get_pins Iregfile/wr_strobe_spi_sync_reg/Q] #gated clocks #create_generated_clock -name "spi_clk_gated"   -divide_by 1  -source [get_ports spi_clk]   [get_pins spi/spi_clk_gate/Q] # Propagate clocks. NOTE: we don't propagate clk, since we don't have any buffers in DC netlist. clks treated as ideal #set_propagated_clock [all_clocks] # Apply false-paths: In false paths, we define false paths # NOTE: false paths only related to setup timing are checked here. If log report indicates an ERROR in any line, it doesn't take any false path from that line into consideration (i.e it doesn't expand the wildcards to choose paths that match and drop paths that don't exist, however PnR tool does expand the wildcards and choose paths that match and drop paths that don't exist, without reporting any error, so be careful). Hold, async, clk-gating paths aren't checked (unconstrained paths) durng synthesis, however they are checked during PnR. so, we might have to add extra false paths when running PnR. These added paths may give ERROR when synthesis is re run, however we can just ignore such errors. Or instead of adding these extra false paths in DC, we can create a new false path file in PnR, and add this file to existing false path file from DC. #set_disable_timing [get_cells {test_mode_dmux/*}] source -echo tcl/false_paths.tcl #set_false_path -from {POR_N POR_N_SYNCED SCAN_RESET} => Not needed as these cause recovery/removal violations which DC doesn't check for. Only scan_en pin needs to be set to false_path as it causes real timing violation due to large transition time. However if scan_en pin is set to ideal_network, then fasle path not needed for scan_en as transition time=0ns. # Apply multi-cycle paths source tcl/multicycle_paths.tcl # Incremental Compile with high effort source tcl/compile.tcl This has: #here we do design rule and opt rule fixing #-incremental performs only gate level opt and not logic level opt. Resulting design is same or better than original. #-map_effort high => default effort is medium. high effort causes restructuring and remapping the logic around critical paths. It changes the starting point, so that local minima problem is reduced. It goes to the extreme, so is very CPU intensive. compile_ultra  -incremental -scan -area_high_effort_script -gate_clock -no_autoungroup

5. generate reports:

#generate reports: report_area, report_reference => in area.rpt report_timing -delay max -max_paths 500 => report setup in max_timing.rpt (this has timing with scan_mode=0, so has all interclock paths) report_timing -delay min -max_paths 500 => report hold in min_timing.rpt => this report should be clean if no clk_uncertainty is defined. This is because c2q delay for flops is greater than hold requirement of flops, so with ideal clock (no clk delays/buffering anywhere), all flops will pass holdtime req. check_design, report_clock_gating, report_clocks, check_timing, report_disable_timing => in compile.rpt report_clock_gating => reports no of registers clk gated vs non-clk gated. It also shows how many CG* cells got added to do clk gating. report_constraint => lists each constraint, and whether met/violated, also max delay and min delay cost for all path groups. -all_violators only reports violating constraints. #cleanup netlist and then write netlist cleanup as done in compile_initial (remove_unonnected_ports, define_name_rules, change_names) write -format verilog -hierarchy -output ./netlist/digtop.v 6. Insert Scan:

#SCAN: DFT compiler (separate license) is invoked for scan. DFTMAX license is needed for scan compression. #Insert Scan set_ideal_network [get_ports scan_en_in] => scan_en_in pin is used during scan shifting (defined in setup.tcl). By setting it as ideal, DFT compiler doesn't buffer the signal as all cells/net on this n/w have "dont_touch" attr set. To buffer it, put driving cell using set_driving_cell on this port, so that DFT Compiler can buffer it appr. In DC, we don't buffer this signal, as we buffer it during PnR. NOTE: if scan_en_in is internal net, we should do this: set_ideal_network -no_propagate {u_DIA_DIG/u_DMUX_DIG/U5/Y} => We should choose gate o/p pin and not the o/p scan_en net ({u_DIA_DIG/u_DMUX_DIG/scan_en}). Else ideal network is not applied to gate o/p, so that gate has large transition time, so tons of viols. #set_false_path -from scan_en_in => setting any path flowing thru Scan_en and ending at clk as false. Since we have set scan_en as ideal n/w, we don't need false path for this as transition time=0ns. However if ideal n/w is not set for scan_en, then this takes care of cases where scan_en i/p delay causes any setup/hold violation at clk. If we don't do this, we see paths with scan_en failing as they have high FO and high cap, so large delay and large transition time.  We can NOT take care of this by setting small max_delay for setup and large min_delay for hold, because the high FO will cause it to fail timing nonetheless. NOTE: this is not equiv to setting case analysis for scan_en=0, as that removes scan paths (flop to flop) from any timing analysis. We want to see timing for both scan/non-scan paths. #IMP NOTE: both false_path and ideal_network for scan_en pin should be removed in EDI (if using sdc constraints generated from DC), since scan_en path is real, as we have clk toggling within a cycle of scan_en toggling in Tetramax patterns, so it better meet timing. We need to run gate sims on teramax patterns to make sure we meet timing. source tcl/insert_dft.tcl => this file has following lines in it: #sets all scan configuration details as shown below: #set test timing variables. leave these at default values if Tetramax is used to gen test patterns. #set test_default_delay 0 #set test_default_bidir_delay 0 #set test_default_strobe 40 #set test_default_period 100 => default scan period is 10MHz. ######define test protocol using set_dft_signal cmd. #set_dft_signal=>Specifies the DFT signal types for DRC and DFT insertion. #-view existing_dft | spec => existing_dft implies that the  specification  refers  to  the existing  usage  of  a port, while spec (the default value) implies that the specification refers to ports that the tool must use during DFT insertion. spec view is prescriptive and specifies actions that must be taken. It indicates that signal n/w doesn't yet exist and insert_dft cmd must add it. An example of this is ScanEn signal (even though ScanEn port exists, the signal n/w is not there, so it's prescriptive). existing_dft view is descriptive and describes an existing signal n/w. An example is system clk that is used as Scan Clk (here clk n/w already exists since system clk is used as scan clk, so descriptive). So, scan_clk, reset, scan_mode are existing_dft as n/w is already there, but SDI, SDO, ScanEn are spec as that n/w needs to be built. view is used for many DFT cmds as set_dft_signal and set_scan_path. Ex: set_dft_signal -view existing_dft -port A -type ScanEnable => when working with dft inserted design, indicates that port A is used as scan enable. indicates that ScanEnable n/w does exist and should be used. This is NOT true in most designs as n/w never exists for scan_en pin. In this case, tool will create a new port "A" and connect it to scan_en pin of all flops Ex: set_dft_signal -view spec -port A -type ScanEnable => when preparing a design for dft insertion, specifies that port A  is used as scan enable. indicates that ScanEnable n/w doesn't exist yet. This is true for most designs, so use this for scan_en pin. #-type specifies signal type, as Reset, constant, SDI, SDO, ScanEn, TestData, TestMode. Constant is a continuously applied value to a port. #-active_state => Specifies the active states for the following signal types: ScanEnable, Reset, constant, TestMode, etc. active sense high or low #define clocks, async set/reset, SDI, SDO, SCAN_EN and SCAN_MODE. We don't need to define SCAN_CLK as SCAN_MODE forces clock to scan clk (mux chooses b/w SCAN_CLK or FUNC_CLK), and it is traced all the way to the i/p port (as later during create_test_protocol, we say -infer_clock). We don't define async set/reset as we force them to 0, when scan_mode=1 (in RTL itself). set_dft_signal -view existing_dft -port scan_mode_in -type Constant -active_state 1  => scan_mode_in pin is used during scan mode and is high throughout scan (defined in setup.tcl). existing_dft states that scan_mode n/w exists so the tool doesn't need to do anything to add the n/w. set_dft_signal -view spec  -port  spi_mosi       -type ScanDataIn => SDI is spi_mosi set_dft_signal -view spec  -port  spi_miso       -type ScanDataOut => SDO is spi_miso set_dft_signal -view spec  -port  scan_en_in     -type ScanEnable  -active_state 1 => SE (for shifting during scan) is scan_en_in, and it needs to be "1" for shifting to take place. If scan_en is an internal pin, then we do:  set_dft_signal -view spec   -hookup_pin {u_DIG_sub/scan_enable} -type ScanEnable  -active_state 1 => pin may be port of sub-module or o/p pin of a gate as "u_DIG_sub/u_sub2/U5/Y". Preferred to use port of sub-module as gate name may change every time tool is run. #NOTE: in all cmds above, if above scan ports don't exist, then tool creates new ports. #if needed, set_dft_signal for scan clk, scan reset and scanmode => NOTE these are "exist" view and not "spec" view set_dft_signal -view exist -type ScanClock   -port SPI_SCK -timing [list 10 [expr ($SCANCLK_PERIOD/2)+10]] => changed freq of scan clk, so that design runs slower set_dft_signal -view exist -type Constant    -port SCANRESET      -active_state 1 set_dft_signal -view exist -type Constant    -hookup_pin {u_SPT_DIG/auto/Scan_Mode_reg/Q}  -active_state 1 =>  Preferred to use port of sub-module for hookup_pin as in extreme case, flop name may change every time tool is run. ####do all scan related configuration. #set_scan_element: excludes seq cells from scan insertion, reducing fault coverage set_scan_element false [find cell test_mode/scan_mode_out_reg] => default is true which means all  nonviolated  sequential  cells  are replaced with equivalent scan cells. when false, no scan replacement done on objects (objects may be cells[as FF/LAT], hier cells, lib cells, ref, design). Sequential cells violated by dft_drc are not replaced by equivalent scan cells, regardless of their scan_element attribute values. # Specify scan style: 4 styles: multiplexed_flip_flop, clocked_scan, lssd, scan_enabled_lssd. set_scan_configuration or test_default_scan_style can be used to set scan style. #set_scan_configuration -style [multiplexed_flip_flop | clocked_scan | lssd |  aux_clock_lssd  | combinational | none] => By default, insert_dft uses the scan style value specified by environment variable test_default_scan_style in your .synopsys_dc.setup file set_scan_configuration -style multiplexed_flip_flop #count set_scan_configuration -chain_count 1 => number of chains that insert_dft is to build. Here's it's 1. If not specified, insert_dft builds the minimum  number of scan chains consistent with clock mixing constraints. #set_scan_configuration -clock_mixing [no_mix | mix_edges | mix_clocks | mix_clocks_not_edges] => Specifies  whether  insert_dft  can include cells from different clock domains in the same scan chain. no_mix                 The default; cells must be clocked by the same edge of the same clock. mix_edges              Cells must be clocked by the same clock, but the clock edges can be different. mix_clocks_not_edges   Cells must be clocked by the same clock edge, but the clocks can be different. mix_clocks             Cells can be clocked by different clocks and different clock edges. set_scan_configuration -clock_mixing mix_clocks => we use mix_clocks even though during scan_mode, we have only 1 clk. Reason is that lockup element can only be added if mix_clocks option is used. #lockup set_scan_configuration -add_lockup true => Inserts  lockup  latches (synchronization element) between clock domain  boundaries  on  scan  chains,  when  set  to  true  (the default). If the scan specification  does  not  mix clocks on chains, insert_dft ignores this option. #lockup_type [latch | flip_flop] => The default lock-up type is a level-sensitive latch.  If you  choose  flip_flop  as  the  lock-up type, an edge-triggered flip-flop is used as  the  synchronization  element. #set_scan_configuration -internal_clocks [single|none|multi] => An internal clock is defined as an internal signal driven  by  a multiplexer (or multiple input gate) output pin (excludes clk gating cells). Applies  only  to  the  multiplexed flip-flop scan style, and is ignored for other scan styles.  It's used to avoid problems when placing gating logic on the clock lines (which might result in hold issues). none (the default) - insert_dft does not treat internal clocks as  separate  clocks.   This  is  the default value for internal_clocks option. single  -  insert_dft treats any internal clocks in the design as separate clocks for the purpose of scan chain architecting.The single value stops at the first buffer or inverter driving the flip-flops clock. multi - insert_dft treats any internal clocks in the design as separate  clocks  for  the purpose of scan chain architecting. The multi value jumps over any buffers and inverters, stopping at the first multi-input gate driving the flip-flops clock. set_scan_configuration -internal_clocks multi => for our design, we set it to multi. #set_scan_link scan_link_name [Wire | Lockup] => Declares  a  scan link for the current design.  Scan links connect scan cells, scan segments, and scan ports within scan chains.  DFT  Compiler supports scan links that are implemented as wires (type Wire) and scanout lock-up latches (type Lockup). set_scan_link LOCKUP Lockup => we name the scanlink LOCKUP #set_scan_path specifies scan path. set_scan_path chain1 => Specifies a name for the scan chain, here it's called chain1 #set_scan_state [unknown|test_ready|scan_existing] => sets the scan state status for the current design. Use this command only on a design that has  been  scan-replaced  using,for example, compile -scan, so that the Q ouputs of scan flip-flops are connected to the scan inputs and the scan enable pins are connected  to logic  zero.   If  there  are  nonscan  elements  in  the  design,  use set_scan_element false to identify them. unknown=>the  scan  state  of  the  design  is  unknown, test_ready=>the design is scan-replaced, scan_existing=>the design is scan-inserted. set_scan_state test_ready --- End of scan_constriants.tcl file. ###### configure your design for scan testing by generating test protocol using create_test_protocol. Test protocol files are written in spf (STIL procedure file) which are then input to pattern generation tools as TetraMax, Encounter Test to generate pattern file in STIL format. #create_test_protocol [-infer_asynch, -infer_clock, -capture_procedure single_clock | multi_clock] => creates a test protocol for the current design based on user specifications which were issued prior to  running  this command.  The   specifications   were  made  using  commands  such  as set_dft_signal, etc. The  create_test_protocol command should be executed before running the dft_drc command because design rule checking requires a test  protocol. -infer_asynch => Infers asynchronous set and reset signals in the design, and places them at off state  during scan shifting. -infer_clock => Infers test clock pins from the design, and pulses them during scan shifting. -capture_procedure [single_clock | multi_clock] => Specifies the capture procedure type.  The multi_clock type creates a protocol file that uses generic  capture  procedures  for all  capture  clocks.   The single_clock type creates a protocol file that uses the legacy 3-vector capture  procedures  for  all capture clocks. The default value is multi_clock. create_test_protocol -infer_clock => -infer_clock not needed if scan_clock defined above. ####DFT DRC Checking dft_drc checks for these 3 violations: -- 1. Violations That Prevent Scan Insertion: caused due to 3 cond:  A. FF clk is uncontrollable. => clk at FF should toggle due to test clk toggling, and clk at FF shoudl be in known state at time=0 (sometimes clk gating causes this issue)  B. latch is enabled at the beginning of the clock cycle C.  C. async controls of registers are uncontrollable or are held active. => if set/reset of FF/latch can't be disabled by PI of design. 2. Violations That Prevent Data Capture: caused due to these:  A. clk used as data i/p to FF,  B. o/p of black box feeds in clk of reg (clk may or may not fire depending on logic),  C. src reg launch before dest reg capture,  D. registered clk gating ckt (caused due to clk gating implemented wrongly)  E. 3 state contention  F. clk feeding multiple i/p of same reg (i.e. clk signal feeding into clk pin and async set/reset) 3. Violations That Reduce Fault Coverage:  A. combo feedback loops (i.e if loops are used as a latch, replace them with a latch)  B. Clocks That Interact With Register Input  C. Multiple Clocks That Feed Into Latches and FF. Latches should be transparent, and latches must be enabled by one clock or by a clock ANDed with data derived from sources other than that clock.  D. black boxes: logic surrounding BB is unobservable or uncontrollable.  --- #dft_drc [-pre_dft|-verbose|-coverage_estimate|-sample percentage] => checks the current design against the test design rules of the scan test implementation specified  by  the  set_scan_configuration -style  command. If design rule violations are found, the appropriate messages are  generated. Perform  test  design  rule  checking on a design before performing any other DFT Compiler operations, such as insert_dft, and after creating a valid test protocol. -pre_dft => Specifies  that  only  pre-DFT  rules (D rules) are checked. By default, for scan-routed designs, post-DFT  rules  are checked; otherwise pre-DFT rules are checked. -verbose => Controls  the  amount  of detail when displaying violations. every violation instance is displayed. -coverage_estimate => Generates a test coverage estimate at the  end  of  design  rule checking. -sample percentage =>  Specifies a sample percent of faults to be considered when estimating test coverage. dft_drc -verbose => check for violations here, before proceeding. shows black box violations for macro, non-scan flop violation because of set_scan_element being set to false, non-scan flops present in design (flops didn't get replaced by their scan equiv because of set_scan_element being set to false or other issues ). It shows final scan flops and non-scan flops. #preview_dft => Previews,  but does not implement, scan style, the test points, scan chains, and on-chip clocking control logic to be added  to  the  current design. The command first generates information on the scan  architecture  that  will be implemented.  In the case of a DFTMAX insertion, preview_dft provides information about the  compressor  being  created,and for basic scan, the specific chain information for the design. Next,  the command generates and displays a scan chain design that satisfies scan specifications on the current  design. This design is exactly the scan chain design that is presented to the insert_dft command for synthesis. preview_dft -show all => Reports  information  for all objects in scan chain design. preview_dft -test_points all => Reports all test points information, in addition to the  summary report  the preview_dft command produces by default.  The information displayed includes names assigned  to  the  test  points,locations  of  violations  being fixed, names of test mode tags, logic states that enable  the  test  mode,  and  names  of  data sources or sinks for the test points. # Insert Scan and build the scan chain. insert_dft => adds internal-scan or boundary-scan circuitry to the  current design. First, the  command  populates  a  flattened  representation  of  the  entire  design. By default, insert_dft performs only scan insertion and routing. Next,  insert_dft architects scan chains into the design. By default, insert_dft constructs as many scan chains as there are clocks  and  edges.   By   setting   the -clock_mixing option, we can control scan chains created. Scan cells are ordered on scan chains based on some criteria. Then the command applies a scan-equivalence process to all cells. The insert_dft command then adds generic disabling logic  where  necessary.   It  finds  and  gates all pins that do not hold the values they require during scan shift.Having  disabled  three-state buses and configured bidirectional ports,insert_dft builds the scan chains. It identifies scan_in and scan_out ports. Finally,  insert_dft  routes  global  signals (including either or both scan enable and test clocks) and applies a default  technology  mapping to  all new generic logic (including disabling logic and multiplexers). It  introduces  dedicated  test  clocks  for  clocked_scan,  lssd,  and aux_clock_lssd scan styles. Typically, at this point, the insert_dft command has  violated  compile design  rules  and  constraints  and now begins minimizing these violations, and optimizing the design. The insert_dft command automatically updates the test protocol after inserting scan circuitry into the design, and dft_drc can be executed  afterward without rerunning create_test_protocol. # DFT DRC Checking after insertion write_test_protocol -output digtop_scan.spf => Writes a test protocol file to file_name specified. dft_drc -verbose -coverage_estimate => verbose rpt with coverage post scan to make sure no violations. Coverage reported here is inferior than one reported by TetraMax/ET as those are more accurate. Also, scan_reset pin if present is not considered in coverage here, as we never provided scan_reset pin info to the tool. It's just tied to inactive state here. #test coverage = detected_faults / (total_faults - undetectable_faults) => This is the important one to look at #fault coverage = detected_faults / (total_faults) => this is always lower than test_coverage as UD faults not included. Not so important one to look at. #report on scan structure: report_scan_chain > reports/scan.rpt report_scan_path -view existing_dft -chain all >> reports/scan.rpt report_scan_path -view existing_dft -cell all >> reports/scan.rpt # reports after scan insertion => redirect cmd used to create scan.area/max_timing/min_timing/compile rpts in reports/scan.compile.rpt/timing.rpt files. Then cleanup done, and verilog file wriiten in *_scan.v file. #we don't run inc compile after scan, as scan cells are only getting stitched, so each Q pin sees a little bit of extra load due to SD pin of next flop. That little extra load causes <0.1ns timing change, so scan timing and func timing are almost same (scan mode is set to 0 for both, scan_enable/shift_enable is not forced). Sometimes, wire from Q to SDI may be significant because may be the next flop in chain is in another block very far away, resulting in large timing violation on such paths in DC (due to large transition time). When we see such paths in DC, we should ignore them as PnR tool will buffer and fix it. NOTE: this scan timing is different that scan timing in PT, as scan timing in PT reflects timing in scan_mode=1. We can run such timing in DC too (by setting scan_mode=1, defining single scan_clk, and setting all i/o delays wrt scan_clk). However, we'll only see hold violations here mostly related to scan_shift_en paths (setup path failures would mostly be same as those of functional paths). #NOTE: dft compiler adds a mux whenever a functional pin is used as SDO pin. Select pin of mux is tied to ScanEnable pin. "0" input is functional o/p, while "1" i/p is connected to o/p pin of last scan chain. That's why after routing scan chains, we see extra mux in digtop.scan.v compared to digtop.v. We need this as functional flop and SDO flop may not be same flop. compiler may decide to have sdo_out from a different flop than func pin flop. If SDO pin of last scan chain is connected directly to func o/p port, then this mux is not reqd. ----------------------------------------------------------------- # Write out SDC (synopsys design constraints) script file in functional mode. This script  contains  commands  that can  be  used  with  PrimeTime  or  with  Design Compiler. This sdc file combines all constraints file (user or auto generated) in func mode and so is used in AutoRoute during func mode. write_sdc sdc/func_constraints.sdc #count total instances in DC netlist /home/kagrawal/scripts/count_instances_EDI.tcl => reports all gates in reports/instance_count.rpt #use exit or quit exit #Final log file is in logs/top.log. Lok in this file for any errors/warning. #Final reports: are in reports dir. Look in #digtop.after_constrain.rpt => all false path, other constraint errors. #digtop.compile/area/max/min for reports with no scan. #digtop.scan.compile/area/max/min for reports with scan. ******************************************* path groups: Look in PT notes (manually written ones) for more details. ---------- by default, DC/PT group paths based on the clock controlling the endpoint (all paths not associated with a clock are in the default path group). We'll see Path Group with "clock_name" in timing reports. #control opt of paths: We can create our own path groups so that DC can optimize chosen critical paths. group_path -name group3 -from in3 -to FF1/D -weight 2.5 => creates group3 path from i/p in3 to FF, and assigns a weight of 2.5 to this path group. default weight is 1 for all paths in a path group. weight can range from 0 to 100. #opt near critical path: by default, only path with WNS is opt. but by specifying critical range, DC can opt all paths that are within that range. group_path -critical_range 3 => opt all paths within 3 units of WNS (i.e if WNS = -15, then paths with -12ns and worse are all opt). can also use "set_critical_range 3.0 $current_design". #opt all paths: create path group for each end point. then DC opt each path group. set endpoints [add_to_collection [all_outputs] [all_registers -data_pins]] => all o/p ports and D pins of all FF added. foreach_in_collection endpt $endpoints {  set pin [get_object_name $endpt]  group_path -name $pin -to $pin } --------------------------- #useful cmds: #To remove design from DC mem, we can do this (instead of closing and opening DC) dc_shell> remove_design -all #Retarting dc shell again. We can read in previous .ddc file generated by using read_ddc cmd. This is helpful when we close dc-shell, but want to open previous design again. dc_shell> read_ddc netlist/digtop_scan.ddc #to remove design from dc_shell. can be used once design has been saved, so that we can start a new run without exiting dc_shell dc_shell> remove_design -all => removes current design as well as all subdesigns from memory #reporting any net connectivity report_net -conn -v -nosplit net1 => reports (v for verbose, nosplit to get all in one line) all pins connected to the net and detailed report of cap. useful for High FO nets. #reporting Fanout for all nets above a certain threhold report_net_fanout -v -threshold 100 => reports (v for verbose) all nets with FO > 100 -------------------

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Day 4 of Trump New York hush money trial

From CNN's Jeremy Herb, Lauren del Valle and Kara Scannell in the courthouse

We've wrapped up our live updates. Learn more about Friday's proceedings by scrolling through the posts below, and return on Monday for more live coverage of Trump's hush money criminal trial .

Man who lit himself on fire outside of the courthouse has died, law enforcement official says

From CNN's John Miller

The man who lit himself on fire outside of the Manhattan courthouse where Donald Trump’s trial was taking place died Friday night, a senior law enforcement official told CNN.

NYPD Chief of Department Jeffrey B. Maddrey said earlier that the man walked into the center of Collect Pond Park, which is directly across from the courthouse.

He opened his backpack and took out pamphlets that he scattered in the park before setting himself on fire.

The man was taken to Cornell Burn Center earlier in critical condition. Police had said they thought it was not likely that he would survive.

Key takeaways from the final day of jury selection in Trump's hush money trial

From CNN's Jeremy Herb and Lauren del Valle

The historic first criminal trial of a former US president begins with opening statements on Monday.

Judge Juan Merchan swiftly  moved through consideration of roughly 200 potential jurors  to find a jury pool of 18 by midday Friday, swearing in 12 jurors and six alternates who will decide Donald Trump’s fate in the New York hush money case.

Here are takeaways from the final day of jury selection:

• The jury is set: Four women and one man were  added to the jury on Friday as five of the six alternates for the case. They will sit in the jury box and will hear the duration of the trial, but they will only be put on the jury should one or more of the 12 jurors be excused from the case. Prosecutors focused their questions in the case on preparing the jurors to accept testimony from less-than-favorable witnesses, like Michael Cohen. Trump’s attorneys, meanwhile, were almost singularly focused on a single question: What did jurors think about Donald Trump?
• Final round of juror questions highlights emotional decision for potential jurors: There were several emotional moments during Friday morning’s questioning of potential jurors, with two jurors telling the judge in the middle of voir dire that they no longer felt they could serve. One female prospective juror who works in sales for a trading company began crying when she was handed the microphone. At one point after that jury had left, another juror raised her hand and told the court she started feeling “high anxiety” as she sat and listened to a line of questioning about the credibility of witnesses.
• Trump is still trying to stop his trial: Despite seating a jury, Trump’s legal team again tried to stop the trial in its tracks with another strategic appeal. In a new motion filed Friday morning, Trump’s lawyers once again asked an appeals court to temporarily halt the trial until they ruled on Trump’s appeal to move the venue of the hush money trial out of Manhattan. The motion was denied.
• A hearing on Trump’s gag order violations is set for Tuesday: Despite Trump’s attempts to delay, opening statements in his criminal trial will begin Monday morning. On Tuesday, the morning will shift to Trump’s discussion of witnesses in the case, as Merchan plans to hold a hearing on social media posts by the former president that prosecutors say violated his gag order. They’re asking the judge to fine Trump $1,000 per post and remind him that violations of the gag order could result in imprisonment.

5 alternate jurors were selected Friday. Here's what we know about them

From CNN's Kara Scannell, Lauren del Valle, and Jeremy Herb

The full panel in Donald Trump's hush money trial has been set after five alternate jurors were selected Friday.

Remember: A full 12-person jury was seated earlier this week, along with one alternate juror.

Here's what we know about the alternate jurors selected Friday:

Alternate Juror #1

• A woman originally from Spain
• Not currently working
• Married with adult children
• Likes to travel
• Says she does not follow the news and does not have any social media accounts
• Says she doesn't "have strong opinions about former President Donald Trump that would interfere" with her ability to be a fair and impartial juror

Alternate Juror #3

• A native New Yorker
• He is a fan of martial arts

Alternate Juror #4

• A contract specialist who has previously lived in New Jersey and Oregon
• She is married with two children
• Says she likes to see live music and take her boys to basketball games
• Says she’s “not a big news person” but looks at The New York Times, Reuters and the BBC
• Does have social media profiles but doesn’t post or use them

Alternate Juror #5

• Works for a clothing company
• Says she gets her news from Google

Alternate Juror #6

• Project manager for a construction company
• She is divorced with three sons
• Her boyfriend is in law enforcement
• Says she listens to true crime podcasts
• Her father was convicted of a federal crime when she was in high school but she said she was shielded from the details

The full jury is sworn in. Catch up on what happened ahead of opening statements in the hush money trial

From CNN staff

The full jury panel has now been seated in the hush money trial against Donald Trump, clearing the way for opening statements to start on Monday.

There are 12 jurors and six alternates who will hear the case against the former president.

Opening statements are set to begin Monday at 9:30 a.m. ET. Court will be a half day on Monday and Tuesday due to Passover, ending at 2 p.m. ET each day.

Leaving the courthouse Friday, Trump again called the trial a "giant witch hunt." Just hours after jury selection finished, an appeals court denied Trump’s latest attempt to stop the trial from going forward.

Here’s what happened today:

Finishing jury selection:

• The remaining five alternates were sworn in on Friday. All 12 jurors and one alternate were selected Thursday.
• The day started with a group of  22 potential jurors answering a questionnaire and facing more questions from lawyers on both sides.
• Trump watched the alternates' answers very closely as they shared their opinions of him, turning toward the jury box as they responded. 
• Before the lunch break, Judge Juan Merchan gave the jurors instructions not to discuss the case with others or research it. He said the court cannot start until all 18 jurors are present each day.

Sandoval hearing:

• The judge held a Sandoval hearing in the afternoon after the full jury was sworn in. The routine procedure aimed to address Trump’s criminal history and assess how much prosecutors can ask about it if the defendant testifies.
• Prosecutors want to bring up past cases — including a $355 million civil fraud order and the E. Jean Carroll defamation case — but the former president's legal team argues those issues aren't relevant to the case at hand .
• The judge said lawyers will have his decision on that matter by Monday.
• It's not yet clear whether the former president will testify. But coming out of the courtroom, Trump said “yes” when asked whether he would take the stand.

Meantime: A New York appeals court judge denied Trump’s motion for an interim stay pending a  change of venue appeal . This was the latest attempt by the former president to stop the hush money trial before opening statements.

Outside the courtroom:

• A man lit himself on fire outside the courthouse , New York Police Chief of Department Jeffrey B. Maddrey said.
• The man walked into the park across the street from the courthouse, throwing flyers into the air , according to Maddrey. He then pulled a canister of what police believe to be an accelerant and lit himself on fire, he said.
• The man is in critical condition at Cornell Burn Unit.
• NYPD Chief of Detectives Joe Kenny said police have not determined if the incident was related to Trump’s trial. He said the man did post about the incident on social media and that his internet presence will be part of the ongoing investigation .

See courtroom sketches from Trump's first criminal trial

No cameras are allowed inside the Manhattan courtroom where Donald Trump's hush money is underway, but sketch artists are capturing the scenes.

Trump’s request for interim stay of criminal trial is denied

From CNN's Lauren del Valle

A New York appeals court judge denied Donald Trump’s motion for an interim stay pending a change of venue appeal of his criminal trial.

This was the latest attempt by the former president to stop the hush money trial right before opening statements, which are set to be heard on Monday.

Judge Marsha Michael gave five minutes for each side to argue their case at the hastily arranged hearing Friday afternoon.

Trump says judge in New York hush money case “wants this to go as fast as possible”

From CNN's Kate Sullivan and Kaanita Iyer

Former President Donald Trump spoke to reporters as he exited the courtroom Friday, and said Judge Juan Merchan, who is presiding over the hush money trial, “wants this to go as fast as possible."

“The trial starts on Monday, which is long before a lot of people thought. The judge wants this to go as fast as possible. That’s for his reasons, not for my reasons,” Trump said.

The former president also called the trial "a giant witch hunt" and railed against people involved in the separate New York civil fraud case — including Judge Arthur Engoron and New York Attorney General Letitia James — to make the case that Democrats are targeting him.

Court has adjourned

The court has adjourned for the day. Opening statements in the hush money trial are expected to begin Monday.

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set_case_analysis command

• Thread starter no_mad
• Start date Feb 16, 2005
• Feb 16, 2005

Full Member level 5

set_case_analysis Hi all, My design has inputs from a register. Meaning, these inputs always fix either at 0 or 1. To synthesize this design, can I set these inputs port with “case_analysis” or is it better to set it as false_path?? Please enlighten me.. -no_mad  

• Feb 17, 2005

Full Member level 4

set_case_analysis input Yes, you can use the command to set these input signals.  

Full Member level 2

set_case_analysis is not working I think it is better not to "set_case_analysis"... set_case_analysis is mostly used for those control pins like, scan enable... These controls pin will modify the mode of the chip's operation, suck as clock distribution, like scan mode. If it is not, do not use set_case_analysis... then DC may consider the timing check more completely...  

set case_analysis hi Tony, So, it is better to use set_false_path unless I want to do a scan chain..  

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‘Criminal Conspiracy’ Alleged as Jury Starts Hearing Trump Trial

Court adjourned for the day after opening statements from both sides and the start of testimony from the longtime publisher of The National Enquirer. A lawyer for Donald Trump told jurors the former president did nothing illegal.

• Share full article

Jesse McKinley and Kate Christobek

Five takeaways from the fifth day of Trump’s criminal trial.

Monday marked another key moment in the criminal trial of Donald J. Trump: opening statements, during which the former president listened quietly to the prosecution’s allegations of crimes, and the defense’s counterargument that he was a simple man, wrongly accused.

The jury that will decide Mr. Trump’s case concentrated intently on the statements, which began the presentation of what will be weeks of testimony and other evidence, all in a tense courtroom in Lower Manhattan.

The presumptive Republican presidential nominee once more, Mr. Trump, 77, is charged with falsifying 34 business records in an attempt to cover up a payment to a porn star, Stormy Daniels, in the days before the 2016 election. Ms. Daniels, who may testify, says that she and Mr. Trump had a sexual encounter in 2006, a claim the former president denies.

Mr. Trump has also denied the 34 felony charges, calling them orchestrated by Democrats; if convicted, the former president could face probation or up to four years in prison.

Here are five takeaways from Mr. Trump’s fifth day on trial:

The prosecution has a big story to tell.

The charges faced by Mr. Trump may sound bland — “falsifying business records” doesn’t really set the heart racing — but the prosecution made clear on Monday that it plans on painting a much broader picture.

Matthew Colangelo, a prosecutor, laid out in his opening statement a tale that touched on tabloid journalism , tawdry affairs and covertly recorded phone calls . Jurors will likely be told about events inside fancy hotel rooms, Trump Tower and even the Oval Office. And the stakes? The presidency.

All that suggests that the case will keep jurors wide-awake during the six or so weeks it is projected to take. Indeed, when asked if they wanted paper and pens to take notes, more than half of the people in the jury box (12 jurors and six alternates) raised their hands.

Who Are Key Players in the Trump Manhattan Criminal Trial?

The first criminal trial of former President Donald J. Trump is underway. Take a closer look at central figures related to the case.

The defense wants to destroy prosecution witnesses.

Mr. Trump’s lead lawyer, Todd Blanche, used his opening statement to cast Mr. Trump’s actions leading to this case as run-of-the-mill business, and said that Mr. Trump is defending himself at trial, just as “any of us would do.”

He argued that the use of a nondisclosure agreement — the document Ms. Daniels signed after receiving the payment — was typical among the wealthy and the famous and “nothing illegal.” He continued that there was nothing wrong with trying to influence an election, adding: “It’s called democracy.”

Mr. Blanche also attacked Mr. Cohen, a former lawyer and fixer for Mr. Trump. He said Mr. Cohen, who pleaded guilty to federal campaign finance crimes in 2018, was a “criminal” who “can’t be trusted.” He added that Ms. Daniels was “biased” against Mr. Trump and made a living off her story about the sexual encounter.

He called the heart of the prosecution case just “34 pieces of paper” that don’t involve Mr. Trump.

Trump was muted during the abbreviated day in court.

On Mr. Trump’s way into the courtroom on Monday, he addressed reporters for about three minutes and blasted a range of perceived enemies, including New York’s attorney general, Letitia James, and the judge in a recent civil fraud case that resulted in a $454 million judgment against him.

But Mr. Trump’s behavior during opening statements reflected that he understood the gravity of the moment.

Mr. Trump made no outbursts during the prosecution’s opening statement, although he occasionally showed displeasure: He shook his head slightly at arguments that he orchestrated a scheme to corrupt the presidential election and then more strenuously when prosecutors said he was guilty of felonies.

During his own side’s opening statement, Mr. Trump sat largely motionless and expressionless watching his lawyer Mr. Blanche. Mr. Trump’s behavior was muted compared with his volatility during past Manhattan court appearances.

But at the conclusion of the trial day, Mr. Trump took his preferred spot in front of a television camera in the hallway, and spoke for more than nine minutes, attacking the prosecutor’s case — once again — as unfair.

David Pecker used to live on celebrity news. Now, he is the news.

Prosecutors’ first witness was David Pecker, the longtime publisher of The National Enquirer . He ambled to the stand and promptly gave a lesson in the ways of tabloid journalism, including the purchasing of articles — anything more than $10,000, he had to approve — and the significance of putting a famous face right out front.

“The only thing that was important is the cover of a magazine,” Mr. Pecker testified.

In about 30 minutes of testimony, Mr. Pecker also laid out trade secrets on sourcing, saying hotel workers and limo drivers could be a font of information on the rich and famous.

He seemed at ease: laughing at a prosecutor’s jokes, and sometimes directly addressing the jury just a few feet away.

We’re moving right along.

Over the past five trial days, the judge overseeing the case, Juan M. Merchan, has shown that he is eager to keep this trial on schedule. He seems serious about keeping his word to the jurors that the trial will last six weeks.

On Monday, truncated by a juror’s dental emergency and the Passover holiday, he decided to start with the first witness — Mr. Pecker — despite having only half an hour left on his schedule.

On Tuesday, the court will first consider a prosecution motion to hold Mr. Trump in contempt over recent comments that they say violated a gag order meant to keep him from attacking participants in the trial and their families.

Then, Mr. Pecker will continue on the stand, probably diving deeper into the “catch-and-kill” scheme used to buy up — and cover up — unflattering stories, a central element of the prosecution’s narrative.

Court will end early again, at 2 p.m., for further observance of Passover and then will have its weekly Wednesday break.

But there is little indication that as the weeks pass, Justice Merchan will let the pace slacken.

Jonah E. Bromwich and Kate Christobek

The opening statements gave a preview of how the two sides will present the case.

The Manhattan district attorney’s office and lawyers for Donald J. Trump presented opening statements to jurors on Monday, with prosecutors accusing the former president of entering a criminal conspiracy while the defense sought to discredit two key witnesses.

A prosecutor, Matthew Colangelo, began by telling jurors that Mr. Trump had conspired with his former fixer, Michael D. Cohen, and the publisher of The National Enquirer, David Pecker, to conceal damaging stories during his 2016 campaign.

“This case is about a criminal conspiracy and a cover-up,” Mr. Colangelo said, telling a story about a hush-money payment to a porn star and insisting that the former president was ultimately responsible.

In the end, Mr. Colangelo said, there would be “only one conclusion: Donald Trump is guilty of 34 counts of falsifying business records in the first degree.”

Immediately after Mr. Colangelo’s presentation, Mr. Trump’s lead lawyer, Todd Blanche, directly disagreed, insisting that the jury acquit the former president. Mr. Trump, he said, had engaged in actions that were legal and normal.

“President Trump did not commit any crimes,” Mr. Blanche told the jury, using the former president’s preferred form of address. The lawyer told jurors that Mr. Trump had earned the right to be referred to as “president” and reminded them that he was the presumptive Republican nominee.

Mr. Blanche argued that there was nothing illegal about nondisclosure agreements, which he said companies, the wealthy and the famous all use frequently. And, he said, prosecutors were wrong to suggest something criminal about Mr. Trump’s efforts to win the White House.

“I have a spoiler alert: There’s nothing wrong with trying to influence an election,” Mr. Blanche said. “It’s called democracy.”

Mr. Blanche asserted that Mr. Cohen, a key prosecution witness, was paid for legal services, and he attempted to undermine Mr. Cohen’s credibility. Mr. Blanche called Mr. Cohen a “criminal” who “can’t be trusted” and suggested that he was testifying only because he didn’t get a job in the Trump administration.

He also took aim at Stormy Daniels, the former porn star who claimed she had sex with Mr. Trump, characterizing her as an opportunist who had used a brief encounter with Mr. Trump related to his reality show, “The Apprentice,” to make huge sums of money.

He added that Ms. Daniels was “biased” against the former president and made a living off her story about the sexual encounter.

Mr. Blanche also sought to minimize the charges, saying the records at the heart of the case were just “34 pieces of paper” that the former president had nothing to do with.

Mr. Trump is accused of falsifying business records — which is a felony if prosecutors can show the records were altered with an intent to commit or conceal a second crime.

A year ago, when the former president was formally charged with 34 felonies, the district attorney, Alvin L. Bragg, told reporters that he did not have to specify what the second crime was, and listed three options. During opening statements, Mr. Colangelo made it clear he believed that the strongest case relied on one of those options: convincing jurors that Mr. Trump concealed the violation of a state law that forbids “conspiracy to promote or prevent an election.”

Justice Juan M. Merchan

Presiding Judge

Joshua Steinglass

Todd Blanche

Trump Lawyer

David Pecker

Former Publisher of The National Enquirer

Michael Cohen

Former Trump Lawyer and “Fixer”

Stormy Daniels

Porn Director, Producer and Actress

Advertisement

There’s some good news for people who want to follow the Trump trial in detail, but can’t make it to the courthouse. The New York state court system has just agreed to publish a transcript of each day’s proceeding by the end of the following day on its website. You can find the daily transcripts here .

Olivia Bensimon

Trump’s motorcade left the courthouse just after 1:05 p.m., wrapping up the trial’s first day of testimony. The view was blocked by an N.Y.P.D. dump truck, to many reporters’ great frustration. Inside Collect Pond Park, across from the courthouse, a lone pro-Trump protester’s “Trump for President ’24” banner flaps meekly in the light breeze.

Jonah Bromwich

The charges against Trump, which accuse him of falsifying records, are felonies because prosecutors say he sought to conceal another crime. Prosecutors had said before the trial that they had a menu of three crimes to choose from. The one they emphasized most strongly today is a violation of state election law: “conspiracy to promote election.” It’s not one of the actual charges, but they say it was baked into the overall crime.

And its worth emphasizing that when the district attorney, Alvin L. Bragg, was first asked about this, at a news conference directly after Trump was formally charged, he said that prosecutors did not have to specify which crime they were alleging Trump concealed. But today, Colangelo took the opposite tack: hitting the word “conspiracy” again and again.

William Rashbaum

With the trial now underway, here’s the People of the State of New York v. Donald J. Trump by the numbers: The case was born as “Investigation No. 2018-00403803 – Investigation Into the Business Affairs of John Doe.” That’s how the Manhattan district attorney’s office identified the six-year inquiry that led to today’s proceedings, with the number and name appearing on subpoenas and the correspondence case. Arrest No. M23613757 was given to Mr. Trump when he surrendered last year on April 4. And when the former president was arraigned later that day, his indictment was given a Docket Number, IND-71543-23, which the court system uses to track the case.

Nate Schweber

A courthouse park becomes a stage, and a sideshow, outside Trump’s trial.

Andrew Giuliani, the son of Donald J. Trump’s former lawyer and a regular strutting presence on the periphery of the courthouse where the former president is on trial, posed for photos inside Collect Pond Park.

Grinning and wearing a campaign jacket, Mr. Giuliani, who has made a career as a right-wing media figure, hugged supporters of Mr. Trump on Monday. From one, he borrowed a flag with Mr. Trump’s face that promotes him for president in 2024.

“Two-thousand twenty-four years in prison!” taunted Ricky Caballero, 56, from Brooklyn. “He owes your dad money. Why you out here supporting him?”

Mr. Caballero wore a tank top with a Puerto Rican flag. He said that was his heritage, and that he remembers watching Mr. Trump lob paper towels at survivors of Hurricane Maria in 2017. Mr. Caballero said he was still furious.

Mr. Giuliani circulated like a celebrity among Mr. Trump’s supporters and ignored Mr. Caballero.

It was one of a number of loud exchanges between supporters and detractors of Mr. Trump that were noticeably monitored by the police. There were no police in the park on Friday, when a man amid a mental health crisis burned himself to death in an anti-government protest.

On Monday, there were six community affairs officers and six regular uniformed officers watching closely for trouble.

At one point, the sound of the national anthem wafted through the park, courtesy of the flute-playing activist Marc Crawford Leavitt.

“I’m just playing and no one can argue with my playing patriotic songs,” he said, a sign decrying Trump as a liar hanging around his neck.

Anusha Bayya contributed reporting.

The judge leaves the stand. We are done with the jurors’ first day of trial.

Trump looks angry as he leaves the courtroom, again patting the bench behind him on the way out. His eyes scan over the reporters seated in the gallery as he goes.

The defense just told us that they did not learn who would be testifying first for the prosecution until about 3 p.m. yesterday. Prosecutors had declined to tell them earlier, given that Trump has made something of a habit of attacking witnesses.

I’m again struck at just how quickly we went today. We started late, and by the end of a very short day had finished both opening statements and started in on our first witness. This trial was expected to last six weeks. It may end even more quickly.

Jesse McKinley

A short day, but we got a sense of the details that the prosecution intends to offer in its case, and the contours of the defense. David Pecker was just starting, and will continue tomorrow at 11 a.m. There’s a hearing on possible gag order violations by Trump tomorrow morning at 9:30 a.m.

Maggie Haberman

Pecker is dismissed from the stand. We expect him back tomorrow.

Justice Merchan tells the jurors about the schedule and asks them, as he will before they leave the courtroom each time, not to discuss the case with anyone and not to read about it. He asks them to put it out of their minds.

Pecker greets someone at the defense table politely as he leaves the room. It’s not clear who.

As he answers Steinglass's questions, Pecker sometimes speaks directly to him, but other times he directs his comments to the jurors. Right now he's describing the types of people tabloids typically use as sources: hotel workers, limo drivers, lawyers.

Trump’s lawyers have sought to cast the tabloid that Pecker presided over as a media company like any other. But Pecker’s comment that they practiced “checkbook journalism,” and his description of their editorial practices, may undermine that argument, as we continue to hear about how the publication operated.

Checkbook journalism is one of the things that sets supermarket tabloids apart from more traditional news outlets.

Kate Christobek

Trump is leaning on the defense table as he listens to Pecker’s testimony. As Pecker talks about the editor meetings, Trump passes notes to two of his lawyers before glaring up at Pecker on the witness stand.

Steinglass has a banter going with Pecker as he asks Pecker to recount his work cell phone number at the time.

That may seem small but it’s important — it’s a good bet that those numbers will come up when evidence is presented.

Steinglass gets a loud cackle from Pecker while asking him his phone numbers. “This isn’t a quiz,” Steinglass says.

As Pecker begins to describe The National Enquirer's editor meetings, it again strikes me that these jurors have a really entertaining case before them. They will be taken into a lot of different environments — these editorial meetings, the Trump campaign and the Trump White House, and small meetings of New York operators in which, prosecutors will argue, the history of the country was shaped.

Jurors appear to be taking copious notes.

“We used checkbook journalism, and we paid for stories,” Pecker says of his time at The National Enquirer. Steinglass, the prosecutor, asks him whether he had "final say" over editorial decisions. Anything over $10,000 for a story, Pecker says, had to be approved by him.

Pecker says in his experience, the only thing that’s important “is the cover” of a magazine.

Michael Rothfeld

A look at how tabloids used ‘catch-and-kill’ to trade on the secrets of celebrities.

“Catch-and-kill” is a term coined by old-time tabloid editors for buying the exclusive rights to stories, or “catching” them, for the specific purpose of ensuring the information never becomes public. That’s the “killing” part.

Why would anyone want to spend money on a story that it never intends to publish? In the world of tabloid journalism, where ethical lines are blurry, deciding what to publish and why is often a calculus that covers favors doled out and chits called in.

David Pecker, the former publisher of The National Enquirer, who also oversaw other tabloids such as Star and lifestyle publications such as Men’s Fitness, was a master of the technique , according to people who have worked for him.

In 2003, Mr. Pecker’s company, American Media Inc., bought several muscle magazines founded by a mentor of Arnold Schwarzenegger, the bodybuilding legend and movie star. When Mr. Schwarzenegger, who was often featured in those magazines, jumped into the recall election to replace California’s governor, Mr. Pecker ordered his staff to buy up negative stories about him in order to protect his investment, former employees said.

Staff members called it “the David Pecker Project.” American Media paid $20,000 to a former mistress of Mr. Schwarzenegger so that she would not speak about their affair — though news of it had previously been published. The company paid another $1,000 to her friend and $2,000 to a man who had a video of Mr. Schwarzenegger dancing lewdly in Rio de Janeiro 20 years earlier. Mr. Schwarzenegger was elected governor.

Mr. Pecker’s publications made deals with other celebrities as well, though not always for money. He traded away dirt about the golfer Tiger Woods in exchange for an exclusive interview in Men’s Fitness in 2007, according to people with knowledge of that episode.

And, according to the prosecutors in the Manhattan trial of Donald J. Trump, Mr. Pecker employed “catch-and-kill” tactics in the 2016 presidential election, paying a doorman and a Playboy model to suppress negative stories about Mr. Trump and boost the candidacy of his longtime associate.

Justice Merchan has shown so far that he is eager to keep this trial on schedule. Court will be adjourned for the day in less than a half an hour, but yet the judge has chosen to start the first witness. He seems serious about keeping his word to the jurors that the trial will last six weeks.

What will be interesting about Pecker’s testimony, if it goes as opening statements suggested it would, is that he won’t really be describing Trump’s involvement in any actual criminal activity. Rather, he will serve as a tour guide to the seamy way in which Trump used The National Enquirer to his political advantage — a storytelling point on the way to alleged criminal activity.

And yet, prosecutors have framed Pecker’s involvement here as part of a “conspiracy.” This could be a risk for them — conspiracy is not one of the charged crimes. And this jury has at least two lawyers.

Who is David Pecker, the trial’s first witness?

The first witness in Donald J. Trump’s criminal is David Pecker, who was the publisher of The National Enquirer, and had traded favors with Mr. Trump since the 1990s.

Mr. Pecker, who was sometimes referred to as the “tabloid king,” had long used his publications to curry favor with Mr. Trump and other celebrities, in exchange for tips or for business reasons. Staff members called Mr. Trump, like other favored stars who were off limits, an “F.O.P.” — “Friend of Pecker.”

Mr. Trump and Mr. Pecker, along with Mr. Trump’s former fixer Michael Cohen, hatched a plan in August 2015 to boost his upstart presidential campaign, prosecutors say. The former Trump allies are each expected to take a turn on the witness stand, giving testimony that could help make him the first president convicted of a felony.

Prosecutors for Alvin L. Bragg , the Manhattan district attorney, will try to show that the hush money payment to a porn star at the center of the trial was part of a larger effort to suppress negative news about Mr. Trump to sway the election. That scheme, they will contend, includes two other deals, both involving Mr. Pecker.

Mr. Trump had announced his presidential campaign in June 2015. The plan the men laid out two months later was simple, according to court documents, interviews with people involved in the events or familiar with them, private communications and other records.

Mr. Pecker would use The Enquirer to publish positive stories about Mr. Trump’s campaign and negative stories about his rivals. He would alert Mr. Trump, through Mr. Cohen, when The Enquirer learned of stories that might threaten Mr. Trump. The Enquirer could buy the rights to those stories in order to suppress them, a practice known in the tabloid world as “catch and kill.”

In late 2015, Mr. Pecker’s company paid $30,000 to suppress a claim by a former doorman at a Trump building who said he had heard Mr. Trump fathered a child out of wedlock — a rumor that was apparently untrue. Then in August 2016, The Enquirer’s parent company paid $150,000 to a former Playboy model, Karen McDougal, to keep her account of an affair with Mr. Trump quiet. Two months later, Mr. Pecker and The Enquirer’s editor helped Mr. Cohen negotiate a $130,000 hush-money payment with Stormy Daniels, the former porn star who also said she had sex with Mr. Trump. He has denied both women’s claims.

Mr. Cohen pleaded guilty to federal campaign finance crimes in 2018.

The Enquirer’s parent company, American Media Inc., made a deal that year to avoid federal prosecution, acknowledging that it had illegally tried to influence the election .

Merchan stops testimony, says he realizes jurors weren’t given writing materials to take notes. At least 10 raise their hands when asked if they’d like some.

This jury is an attentive crew, if the number of note-takers is any indication.

Joshua Steinglass, a prosecutor, will question Pecker. He begins by asking him how old he is, apologizing for asking the question. Pecker is 72, married for 36 years. He begins to talk about his biography, starting with his educational background.

David Pecker is the first witness for the prosecution, and their choice looks to be a good one for them. The National Enquirer’s master of “Catch and Kill,” he was part of the conspiracy that Colangelo described in his opening statement, working with Trump and Cohen to bury negative stories about Trump and publish negative ones about his rivals. He’s expected to tell the jury about his conversations with Trump and Cohen about killing the bad stories, including the one about Stormy Daniels. And he’ll provide much of the broad arc of the case – and the motive — corroborating elements of Cohen’s expected testimony along the way.

The judge instructs the people to call their first witness and as expected, they call David Pecker.

With opening statements and a witness, we are squeezing a full day into this half day. Pecker enters. He’s got a trim white mustache and is wearing a grey suit. His grey hair hits his collar. He heads to the witness stand and is sworn in with his hand raised.

Pecker has aged considerably over the last several years. He spells his name and gives his place of residence.

Trump has some support from a group of his lawyers — Alan Garten, the Trump Organization general counsel is here, and the pool reporters saw Alina Habba and Chris Kise in the hallway.

Meet the team defending Donald J. Trump in his criminal trial.

Donald J. Trump has assembled a team of defense lawyers with extensive experience representing people charged with white-collar crimes to defend him against the charges filed by the Manhattan district attorney’s office. Some have worked for Mr. Trump for years. Others are more recent additions, but are involved in the former president’s broader legal defense, also representing him in other criminal cases.

Here’s a look at Mr. Trump’s defense team:

Mr. Blanche started representing Mr. Trump last year, leaving a prestigious position as a partner at Wall Street’s oldest law firm to take him on as a client. He is also representing Mr. Trump in his federal classified documents case in Florida and his federal election interference case in Washington.

Mr. Blanche has also represented Paul Manafort, Mr. Trump’s former campaign chairman, as well as Boris Epshteyn, an adviser to Mr. Trump. Before turning to private practice, Mr. Blanche was a federal prosecutor in the Southern District of New York, where he supervised violent-crime cases.

Susan Necheles

Ms. Necheles has been a lawyer for Mr. Trump since 2021 and represented the Trump Organization during its criminal tax fraud trial in Manhattan. The business was convicted of 17 felonies and ordered by Justice Juan M. Merchan to pay the maximum penalty of $1.6 million.

Ms. Necheles previously represented defendants in major organized-crime and public-corruption cases, including Venero Mangano, the Genovese crime family underboss who was known as Benny Eggs.

Mr. Bove, the newest addition to Mr. Trump’s legal team, is a legal partner to Mr. Blanche. He is a former federal prosecutor for the Southern District of New York who turned to private practice and now represents defendants charged with white-collar crimes.

Gedalia Stern

Mr. Stern is a law partner to Ms. Necheles and also defended the Trump Organization in its criminal tax-fraud trial. He has previous experience representing clients charged with bribery, fraud and conspiracy.

If Trump testifies, he can be grilled about cases he lost and gag order violations.

The judge in Donald J. Trump’s criminal trial ruled on Monday morning that prosecutors could ask the former president about a range of previous cases that he has lost, as well as past violations of gag orders, in the event that he decides to testify in his defense.

Among other cases, the ruling by the judge, Juan M. Merchan, would allow prosecutors to question Mr. Trump about the civil fraud case brought by the New York attorney general, Letitia James, in which the former president was found to have inflated his net worth to obtain favorable loans. That case resulted in a $454 million judgment against Mr. Trump .

Justice Merchan will also allow the Manhattan district attorney’s office — which brought the case against Mr. Trump — to question him about civil cases brought by the writer E. Jean Carroll. Those cases found that Mr. Trump was liable for sexually abusing and defaming Ms. Carroll in the first instance and for defamation in the second. (Justice Merchan did not mention the sexual abuse finding, only the defamation, in his ruling regarding the Carroll cases on Monday.)

Justice Merchan will also let prosecutors ask about Mr. Trump’s attack on a law clerk in a civil fraud case , in violation of a gag order, as well as a 2018 decision that led to the dissolution of the Donald J. Trump Foundation to resolve a case brought by the New York attorney general at the time , Barbara Underwood, over financial irregularities.

The former president suggested in early April that he would testify in the criminal trial , saying that prosecutors “have no case.” That said, Mr. Trump has promised to testify in previous cases only to back out, and Justice Merchan’s decision could change his thinking on such a maneuver.

Justice Merchan said that, in the event that Mr. Trump did testify, he would give jurors “careful and specific” instructions about the scope of prosecutors’ queries, adding that he had “greatly curtailed” what specifics could be the target of questions.

However, Justice Merchan warned Mr. Trump that his ruling was “a shield and not a sword” and that the former president’s testimony could open “the door to questioning that has otherwise been excluded.”

Mr. Trump is being tried on charges that he falsified business records to cover up a hush-money payment to a porn star ahead of the 2016 election. He has denied the charges.

Meet the team prosecuting Donald J. Trump.

The Manhattan district attorney, Alvin L. Bragg, has assembled an accomplished team to take on perhaps the most high-profile case in his office’s history: the first criminal trial against former President Donald J. Trump. The group includes veteran prosecutors and former white-collar criminal defense lawyers who have extensive experience going up against Mr. Trump.

Here’s a look at the prosecution team:

Joshua Steinglass, Senior Trial Counsel

Mr. Steinglass, who has served as an assistant district attorney since 1998, is a recent addition to this case; in 2022 he helped lead the team that secured a conviction against the Trump Organization for conspiracy, criminal tax fraud and falsifying business records. He typically prosecutes significant violent crimes, such as a violent brawl on the Upper East Side that led to the conviction of two Proud Boy extremists in 2019.

Susan Hoffinger, Chief of the Investigations Division

After starting her career at the Manhattan district attorney’s office, Ms. Hoffinger founded her own firm and spent 20 years as a defense lawyer focusing on white-collar criminal defense. She rejoined the district attorney’s office in 2022 and worked with Mr. Steinglass to obtain the conviction of the Trump Organization in its criminal tax fraud trial.

Christopher Conroy, Senior Adviser to Investigations Division

A prosecutor for 28 years, Mr. Conroy previously led the Manhattan district attorney’s office’s major economic crimes unit, where he was involved in the prosecution of the bankrupt law firm Dewey & LeBoeuf and supervised investigations into multinational financial institutions for falsification of business records. Mr. Conroy is the longest serving member of this trial team.

Matthew Colangelo, Senior Counsel to the District Attorney

Mr. Colangelo joined the district attorney’s office in 2022 after serving for two years as a senior official at the U.S. Department of Justice. He previously worked for the New York attorney general’s office, where he oversaw the investigation into the Trump Foundation, which led to its dissolution . He was also, for a time, one of the lead lawyers on the civil fraud inquiry into Mr. Trump.

Rebecca Mangold, Assistant District Attorney

Before joining Mr. Bragg’s major economic crimes unit in 2022, Ms. Mangold clerked for a U.S. District Court judge in New Jersey and worked in private practice for over 10 years. As a partner at the law firm Kobre & Kim, Ms. Mangold focused on criminal and regulatory investigations related to financial misconduct.

Katherine Ellis, Assistant District Attorney

Ms. Ellis joined the Manhattan district attorney’s office in 2018 after working as an associate at Cleary Gottlieb Steen & Hamilton. Before becoming a lawyer, Ms. Ellis worked as a legal analyst at Goldman Sachs, the investment bank.

Ben Protess and Alan Feuer

The landmark case won’t play out in front of TV cameras.

The Manhattan criminal trial of Donald J. Trump will be closely followed around the world. But you will not be able to watch the proceedings on TV.

There will be no video feed aired live from the courtroom. Nor will there be an audio feed, as some federal courts allow.

New York courts generally do not permit video to be broadcast from courtrooms, although a feed is being transmitted into an overflow room for the reporters covering the trial. And cameras will be stationed in the hallway outside the courtroom to capture Mr. Trump’s remarks as he enters and leaves.

Shortly after court adjourned on Monday, the state’s chief administrative judge, Joseph A. Zayas, issued a statement saying that transcripts of each day of the trial would be published online by the end of the following day on the court system’s website .

Judge Zayas was responding to a request for public transcripts filed last week by a New York lawyer, Jim Walden, on behalf of a civic group and the news website New York Focus.

“With current law restricting the broadcasting of trial proceedings and courtroom space for public spectators very limited, the release of the daily transcripts on the court system’s website is the best way to provide the public a direct view of the proceedings in this historic trial,” Judge Zayas wrote in his statement.

Court will be in session, for the most part, every weekday except Wednesdays, from 9:30 a.m. to 4:30 p.m., until the trial ends.

Jonah E. Bromwich and Ben Protess

Here’s the latest in the trial.

Prosecutors in the first criminal trial of an American president began laying out their case for a jury of 12 New Yorkers on Monday, saying Donald J. Trump engaged in a conspiracy to cover up a sex scandal in order to get elected president in 2016.

The first witness called was the tabloid publisher David Pecker, whom prosecutors described as one member of a three-man plot to conceal damaging stories — including a porn star’s account of a sexual tryst — as Mr. Trump mounted his bid for the presidency.

Mr. Pecker was on the stand for only a few minutes in the afternoon before court adjourned for the day. He described how his publication, The National Enquirer, paid for stories, a practice he called “checkbook journalism.” He is expected to return to the stand on Tuesday.

Matthew Colangelo, one of the prosecutors for the Manhattan district attorney’s office, told the jury in his opening statement that the case was about “a criminal conspiracy and a coverup,” describing how Mr. Trump, his longtime counsel Michael D. Cohen, and Mr. Pecker engaged in a strategy to “catch and kill” negative stories.

The lead lawyer for Mr. Trump, Todd Blanche, insisted in his opening statement that the former president had done nothing wrong. “President Trump is innocent,” he told the jury. “President Trump did not commit any crimes.”

The case centers on a $130,000 hush-money payment that Mr. Cohen made to a porn star, Stormy Daniels, to buy her silence as the 2016 campaign was winding down. Prosecutors say he was reimbursed by Mr. Trump, and Mr. Trump falsified business records to conceal his conduct.

Mr. Colangelo said the payment to Ms. Daniels came on the heels of another scandal — the “Access Hollywood” tape, on which Mr. Trump bragged about groping women. Ms. Daniels’s account, he said, “could have been devastating to his campaign.”

He added, “With pressure mounting and Election Day fast approaching, Donald Trump agreed to the payoff and directed Cohen to proceed.”

Mr. Cohen, who was an executive vice president at the Trump Organization and counsel to Mr. Trump, and Mr. Pecker are expected to be central witnesses.

Mr. Blanche attacked Mr. Cohen’s credibility, saying that his livelihood hinges on attacking the former president, and insisted that prosecutors were attempting to present perfectly legal activities, such as entering into nondisclosure agreements, in a negative light.

He continued: “They put something sinister on this idea as if it were a crime. You’ll learn it’s not.”

Here’s what else to know about the trial:

The Manhattan criminal case against Mr. Trump was unveiled a year ago by the district attorney, Alvin L. Bragg. Mr. Trump was charged with 34 felony counts of falsifying business records and if convicted could face up to four years in prison . Those are felonies because prosecutors say Mr. Trump sought to conceal another crime. On Monday, they strongly emphasized a violation of state election law — conspiracy to promote election — that is not one of the actual charges, but they say is baked into the overall crime.

The case is the former president’s first criminal trial, although he has been indicted three other times in three other cities. With those other cases tied up in appeals and other delays, the Manhattan case may be the only one he faces before the 2024 presidential election. The trial is expected to last six weeks.

Before opening statements, the judge overseeing the case delivered a crucial ruling that determined what prosecutors can question Mr. Trump about should he decide to take the stand in his own defense. The ruling, a significant victory for prosecutors that might prompt Mr. Trump to decide not to testify, allows them to question him about several recent losses he suffered in unrelated civil trials, including a fraud case this year in which the former president was found liable for conspiring to manipulate his net worth and was penalized $454 million.

The jury was drawn from a pool of residents of Manhattan, where Mr. Trump is deeply unpopular; during jury selection, dozens of prospective jurors were excused because they said they could not be impartial. But the jurors who were selected each pledged to decide the case based only on the facts. Read more about them.

The case will receive vast media attention, but the proceedings won’t be shown on television .

Dismissed prospective jurors describe intense days in a glaring spotlight.

Follow our live coverage of Trump’s hush money trial in Manhattan.

The two Manhattan residents were led into the courtroom to fulfill a foundational civic duty: to be interviewed as prospective jurors.

But in the room when they arrived was a defendant, Donald J. Trump, unlike any in American history.

Both would-be jurors, a man and a woman, were eventually excused. But the experience thrust them into the spotlight in a way they never had imagined.

One was challenged by Mr. Trump’s lawyers over his past social media posts relating to the former president. The other has a medical practice that she could not shut for six weeks while serving on the jury.

While they were not chosen as jurors, their experiences illustrate the intensity of the attention focused on Mr. Trump’s trial — and on the first jury to ever weigh the fate of a former United States president in a criminal proceeding.

Both contacted The New York Times only after they were excused from serving. Though the court’s rules protecting prospective jurors’ identities end when they are dismissed from serving, The Times is withholding their names and most identifying characteristics about them.

Like the other prospective jurors who were considered, both included detailed personal information on the juror questionnaires they filled out, including where they work.

They were made to answer those questions by speaking into a microphone in open court; soon, both were blindsided as details of their lives ricocheted around the internet. They said they were frustrated that so much attention was devoted to prospective jurors and ascertaining information about them.

While they later learned that the judge in the case, Justice Juan M. Merchan, had ordered the redaction of some of the information jurors were ordered to reveal publicly, they felt that he had acted too late. As with many things connected to the trial, the rhythms and even some of the parameters are being written in real time.

Their experiences mirrored some that other prospective jurors who were dismissed have described. One, a man who gave his name as Mark to NBC News, said he had “satirized Mr. Trump often in my artwork,” and because of that, he had expected not to be chosen.

A woman who gave her name as Kara, who said the nature of her job made serving extremely difficult, told NBC News that she realized the gravity of serving on any criminal jury, but particularly this one.

Seeing Mr. Trump in person, she said, was “very jarring.” He was, she realized, just “another guy.”

One of the prospective jurors who spoke with The Times, the man, did not immediately realize what case he was involved in when he was led into the courtroom on the 15th floor of the Manhattan criminal courthouse. The woman had a sense a week earlier, having read a news story about the trial beginning the week she was supposed to respond to a juror summons.

The man, sitting a few rows behind the prosecutors’ table when the two were part of the first panel of 96 prospective jurors brought into the courtroom Monday afternoon, felt a sense of calm about five minutes into being there. Trump was simply a defendant, he thought. It was a business-records trial. Prosecutors were on one side, the defense lawyers on the other.

The woman was struck by the fact that Mr. Trump stood and waved to prospective jurors, she said, as he and his lawyers were introduced to the group. It felt more to her like the behavior of a campaigning candidate than of a criminal defendant. (Mr. Trump, of course, is both.)

Both were put off by efforts by Mr. Trump’s lead lawyer, Todd Blanche, to assess prospective jurors’ views of Mr. Trump. The man said Mr. Blanche seemed “folksy” in a way he found disingenuous, while the woman was sharper, describing a “witch hunt” to root out people sympathetic to Democrats on the panel — a phrase Mr. Trump uses often to criticize the various prosecutors investigating his conduct.

The man in particular was frustrated that he was asked about past social media posts in which he had been critical of Mr. Trump, which Mr. Blanche’s team raised and which Justice Merchan ultimately agreed meant the man should be excused.

The man believed he could have been fair and resented the implication that he could not have been. Both he and the woman, who said they believed in the system of jury service, noted that they had begun the day taking sworn oaths vowing to render a fair and impartial judgment on the evidence. The man believed his own views — especially views from years ago — had no bearing on his ability to judge the evidence. If anything, he said, he would have been hyper-conscious in doing so.

Both had realized the magnitude of what serving on that jury would mean.

But they were also conscious of the threats and blowback that could come with weighing evidence against Mr. Trump — particularly with their personal details traceable in public. And both had concerns about being chosen because of that; the man in particular said his spouse had been worried.

Both would have valued being part of the historic trial. But both also had a sense of relief that they were not picked.