FPGA Architecture: Principles and Progression

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On-orbit real-time variational image destriping: FPGA architecture and implementation

Fpga architecture and design flow, distributed nonlinear-polynomial computing based on a group of polynomials over a galois field in the fpga architecture, research on machine learning optimization algorithm of cnn for fpga architecture, maple: a machine learning based aging-aware fpga architecture exploration framework, koios: a deep learning benchmark suite for fpga architecture and cad research, hardware software co-design based cpu-fpga architecture: overview and evaluation, unidirectional multi-bit fpga architecture for area efficient implementation of datapath circuits.

Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented application that are designed to process multiple-bit wide data. Studies have shown that the regularity of these multi-bit signals can be effectively exploited to reduce the implementation area of datapath circuits on FPGAs that employ the traditional bidirectional routing. Most of modern FPGAs, however, employ unidirectional routing tracks which are more area and delay efficient. No study has investigated the design of multi-bit routing resources that can effectively transport multiple-bit wide signals using unidirectional routing tracks. This paper presents such an investigation of architectures which employ multi-bit connections and unidirectional routing resources to exploit datapath regularity. It is experimentally shown that unidirectional multi-bit architectures are 8.6% more area efficient than the conventional architecture. Additionally, this paper determines the most are efficient proportion of multi-bit connections.

The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

In this work, a bus encoding method is proposed that reduces the effect of crosstalk. The crosstalk usually occurs when the data is in parallel communicated. In planar structures, the crosstalk effect is large due to the usage of parallel communication and wide data patterns. In bus technique, the huge amount of wires is laid in equal over a significant time. One way to reduce crosstalk without changing the parallel communicating data lines is to reduce the wideband data patterns so as to reduce the power utilization. The proposed encoding method can minimize the crosstalk by reducing wide data patterns without degrading the performance. The architecture is implemented on Artix 7 FPGA at a 28nm technology node. The simulation is done using the HDL tool and the results are compared with the existing FPGA architecture. With the proposed method, the wire density and the power consumption are reduced by 57.4% and 50% respectively as compared with existing 45 nm technologies.

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The International Conference on Image, Vision and Intelligent Systems (ICIVIS 2021) pp 59–65 Cite as

A Survey of FPGA-Based Deep Learning Acceleration Research

  • Ziyi Lv   ORCID: orcid.org/0000-0002-9676-7833 40 , 41 &
  • Jing Zhang   ORCID: orcid.org/0000-0002-0171-0683 40 , 41  
  • Conference paper
  • First Online: 03 March 2022

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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 813))

In a range of fields such as emotion detection, medical image processing and speech recognition, deep learning has recently achieved good results. With the pursuit of more precise results, many scholars try to add more new type network layers to increase the size of the neural network. However, this will lead to deeper and more intricate network models, and training and evaluating models requires intensive CPU calculations and tremendous computing resources which cannot be achieved by general purpose processors. Nowadays, some hardware accelerators such as Field Programmable Gate Array (FPGA) have been employed to accelerate the neural network, and FPGA with reconfigurability and low power consumption are currently applied to improve throughput of deep learning networks at a reasonable price. In this paper, the typical technologies and methods of accelerating deep learning network on FPGA in recent years are reviewed and analyzed with their advantages and disadvantages, and feasible research suggestions for the next research direction are given. It is expected that it will have a certain reference value for researchers in the field of deep learning acceleration and hardware optimization.

  • Hardware accelerator
  • FPGA accelerator
  • Deep learning

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Yann, L., Yoshua, B.: Convolutional networks for images, speech, and time series. Handb. Brain Theory Neural Netw. 3361 (10) (1995)

Google Scholar  

Xingjian, S., Zhourong, C., Hao, W., et al.: Convolutional LSTM network. In: Proceedings of the 27th International Conference on Neural Information Processing Systems, A Machine Learning Approach for Precipitation Nowcasting, pp. 2672–2680. MIT Press (2015)

Ian, J.G., Jean, P.-A., Mehdi, M., et al.: Generative Adversarial Nets. MIT Press (2014)

Jiantao, Q., Song, S., Yu, W., et al.: Going deeper with embedded FPGA platform for convolutional neural network. In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 26–35. ACM (2016)

Chen, Z., Peng, L., Sun, G., et al.: Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 161–170. ACM (2015)

Williams, S., Waterman, A., Patterson, D.: Roofline: an insightful visual performance model for multicore architectures. Commun. Assoc. Comput. Mach. 52 (4), 65–76 (2009)

Xuelei, L., Liangkui, D., Li, W., Fang, C.: FPGA accelerates deep residual learning for image recognition. In: 2017 IEEE 2nd Information Technology, Networking, Electronic and Automation Control Conference (ITNEC). IEEE, Chengdu (2017)

Roberto, D., Griffin, L., Jasmina, V., Paul, C., Graham, T., Shawki, A.: Caffeinated FPGAs: FPGA framework for convolutional neural networks. In: 2016 International Conference on Field-Programmable Technology (FPT). IEEE, Xi’an (2017)

Chao, W., Junneng, Z., et al.: Hardware implementation on FPGA for task-level parallel dataflow execution engine. IEEE Trans. Parall. Distrib. Syst. 27 (8), 2303–2315 (2016)

Article   Google Scholar  

Chen, Z., Di, W., Jiayu, S., Guangyu, S., Guojie, L., Jason, C.: Energy-efficient CNN implementation on a deeply pipelined FPGA cluster. In: Proceedings of the 2016 International Symposium, pp. 326–331 (2016)

Hector A.G., Shahzad, M., Jerald, Y., Ibrahim M.E.: BioCNN: a hardware inference engine for EEG-based emotion detection. IEEE Access 140896–140914 (2020)

Lei, G., Chao, W., Xi, L., Huaping, C., Xuehai, Z.: MALOC: a fully pipelined FPGA accelerator for convolutional neural networks with all layers mapped on chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11), 2601–2612 (2018)

Ming, X., Zunkai, H., Li, T., Hui, W., Victor, C., Yongxin, Z., Songlin, F.: SparkNoC: an energy-efficiency FPGA-based accelerator using optimized lightweight CNN for edge computing. J. Syst. Archit. 115 (4), 101991 (2021)

Gan, F., Zuyi, H., Song, C., Feng, W.: Energy-efficient and high-throughput FPGA-based accelerator for Convolutional Neural Networks. In: 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, Hangzhou (2017)

Dong, W., An, J., Xu, K.: PipeCNN: an OpenCL-based FPGA accelerator for large-scale convolution neuron networks. CoRR 1611 (02450) (2016)

Kaiyuan, G., Lingzhi, S., Jiantao, Q., et al.: Angel-eye: a complete design flow for mapping CNN onto embedded FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (1), 35–47 (2017)

Liqiang, L., Yun, L., Qingcheng, X., Shengen, Y.: Evaluating fast algorithms for convolutional neural networks on FPGAs. In: 2017 IEEE 25th Annual International Symposium on Field-programmable Custom Computing Machines. IEEE, Napa (2017)

Yufei, M., Yu, C., Sarma, V., Jae-sun, S.: Optimizing the convolution operation to accelerate deep neural networks on FPGA. IEEE Trans. Very Large-Scale Integr. (VLSI) Syst. 26 (7), 1354–1367 (2018)

Lei, G., Chao, W., Xi, L., Huangping, C., Xuehai, Z.: A power-efficient and high-performance FPGA accelerator for convolutional neural networks. In: Proceedings of the 12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, pp. 1–2 (2017)

Chao, H., Siyu, N., Gengsheng, C.: A layer-based structured design of CNN on FPGA. In: 2017 IEEE 12th International Conference on ASIC (ASICON). IEEE, Guiyang (2017)

Waichi, F., Kaiyen, W., Nicolas, F., Yunlun, H., Yude, H.: Development and validation of an EEG-based real-time emotion recognition system using edge AI computing platform with convolutional neural network system-on-chip design. IEEE J. Emerg. Sel. Top. Circ. Syst. 9 (4), 645–657 (2019)

Jing, M., Chen, L., Zhiyong, G.: Hardware Implementation and optimization of tiny-YOLO network. Springer, Singapore (2017)

Ke, X., Xiaoyun, W., Dong, W.: A scalable OpenCL-based FPGA accelerator for YOLOv2. In: 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, San Diego (2019)

Hiroki, N., Masayuki, S., Shimpei, S.: A demonstration of FPGA-based you only look once version2 (YOLOv2). In: 2018 28th International Conference on Field Programmable Logic and Applications (FPL). IEEE, Dublin (2018)

Hiroki, N., Haruyoshi, Y., Tomoya, F., Shimpei, S.: A lightweight YOLOv2: a binarized CNN with a parallel support vector regression for an FPGA. In: Proceedings of the 2018 ACM/SIGDA International Symposium, pp. 31–40. ACM (2018)

Chaoyang, Z., Kejie, H., Shuyuan, Y., Ziqi, Z., Hejia, Z., Haibin, S.: An efficient hardware accelerator for structured sparse convolutional neural networks on FPGAs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 1–13 (2020)

Zixiao, W., Ke, X., Shuaixiao, W., Li, Liu., Lingzhi, L., Dong, W.: Sparse-YOLO: hardware/software co-design of an FPGA accelerator for YOLOv2. IEEE Access 8 (99), 116569–116585 (2020)

Xianchao, X., Brian, L.: FCLNN: a flexible framework for fast CNN prototyping on FPGA with OpenCL and Caffe. In: 2018 International Conference on Field-Programmable Technology (FPT). IEEE, Naha (2018)

Caiwen, D., Shuo, W., Ning, L., Kaidi, X., Yanzhi, W., Yun, L.: REQ-YOLO: a resource-aware, efficient quantization framework for object detection on FPGAs. In: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 33–42 (2019)

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Acknowledgements

This research is supported by: (1) 2020-2022 National Natural Science Foundation of China under Grand (Youth) No. 52001039 (2) 2020-2022 Funding of Shandong Natural Science Foundation in China No. ZR2019LZH005.

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Lv, Z., Zhang, J. (2022). A Survey of FPGA-Based Deep Learning Acceleration Research. In: Yao, J., Xiao, Y., You, P., Sun, G. (eds) The International Conference on Image, Vision and Intelligent Systems (ICIVIS 2021). Lecture Notes in Electrical Engineering, vol 813. Springer, Singapore. https://doi.org/10.1007/978-981-16-6963-7_5

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Call for Papers – FPGA 2024

32nd acm/sigda international symposium on field-programmable gate arrays, march 3 – 5, 2024, submission site: https://fpga24.hotcrp.com, abstracts due:   october 6, 2023, submissions due: october 13, 2023.

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2024, the 32nd edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.

Paper Submissions (with and without artifacts)

We solicit research papers related to the following areas:

  • FPGA Architecture : Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
  • FPGA Circuit Design : Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory or nano-scale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability.
  • CAD for FPGAs : Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
  • High-Level Abstractions and Tools for FPGAs : General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
  • FPGA-based and FPGA-like Computing Engines : Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
  • Applications and Design Studies : Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.

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A paper submitted as either regular or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).

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Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/ . LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LaTeX link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract and paper submissions in PDF must be received by 11:59 PM AoE (Anywhere-on-Earth time zone).

Submissions will be considered for acceptance as regular or short papers. A paper submitted to the regular or short category will only be considered in that category. Regular or short submissions will also be considered for acceptance as a poster. Once a paper has been submitted, its authorship list is considered to be fixed and final.

By submitting articles to an ACM Publication, authors are hereby acknowledging that they and their co-authors are subject to all ACM Publications Policies (https://www.acm.org/publications/policies), including ACM’s new Publications Policy on Research Involving Human Participants and Subjects (https://www.acm.org/publications/policies/research-involving-human-participants-and-subjects). Alleged violations of this policy or any ACM Publications Policy will be investigated by ACM and may result in a full retraction of their paper, in addition to other potential penalties, as per ACM Publications Policy.

Authors should ensure that they and their co-authors obtain an ORCID ID (https://orcid.org/register), so that they can complete the publishing process for accepted papers. ACM has been involved in ORCID from the start and ACM has recently made a commitment to collect ORCID IDs from all of their published authors (https://authors.acm.org/author-resources/orcid-faqs). The collection process has started and will roll out as a requirement throughout 2023. ACM is committed to improve author discoverability, ensure proper attribution, and contribute to ongoing community efforts around name normalization; authors’ ORCID ID will help in these efforts.

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The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. References to the authors’ prior work should be made in the third person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as “Removed for blind review,” but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission. When necessary, authors should cite widely-available Open Source software website(s) without claiming ownership. Grant numbers and other government markings should also be blinded during the review process. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged. Similarly, if a paper can be unblinded by active search, this is not considered to undermine the spirit of the double-blind review. However, there are resources to blind open-source repositories for review, including: https://github.com/tdurieux/anonymous_github .

If you have questions about how to meet these guidelines, please contact the program chair before the submission deadline.

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During paper submission, all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is left undeclared or a nonexistent conflict is declared in an attempt to manipulate the review process, the submission may be rejected.

For more information about the ACM Conflict of Interest Policy, see: https://www.acm.org/publications/policies/conflict-of-interest

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Papers submitted are guaranteed by the authors to be unique manuscripts and not previously published, currently accepted or under consideration for acceptance at another venue. They cannot be substantially similar to any other current/future conference, journal, or workshop submission(s) unless the content appeared at a venue that does not have archived proceedings.

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The conference review process includes a rebuttal phase for authors to provide an optional response to reviewers’ questions and comments. This information is considered during the final deliberation process.

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Authors of this year’s best manuscripts will be eligible for the conference’s best paper awards. They will also be invited to extend their work for consideration in a special issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS).

The conference will allow authors to submit accompanying artifacts for their paper submissions for evaluation. This process will allow ACM recognized badges to be associated with the final publication. The inclusion of artifacts with a submission is not required for a paper submission nor will any preference be given to submissions with artifacts over those without. Papers and artifacts will be subjected to separate and independent review processes. Artifact evaluation must NOT interfere with the double blind reviewing process of their accompanying papers, so all accompanying links in the paper to the artifacts should be blinded. All authors will be required at the time of paper submission to indicate if there will also be associated artifacts for evaluation. If artifacts will be included, a descriptor of their nature will be required.

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Kassas, colleagues earn prestigious IEEE research paper award

Each year, one article published in the monthly  IEEE Aerospace and Electronic Systems (AESS) Magazine  is chosen as the recipient of the Harry Rowe Mimno Award. Electrical and Computer Engineering Professor Zak Kassas  received  the most recent award for his paper titled “ I am not afraid of the GPS jammer: resilient navigation via signals of opportunity in GPS-denied environments .”

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IEEE Enacts Ban on 'Lenna' Image from Playboy in Research Papers to Foster Inclusivity

T he IEEE Computer Society announced to its members on Wednesday that, effective April 1, it will no longer accept papers containing the commonly used image of Lena Forsén, a Playboy model from 1972. Known as the “Lenna image,” this image has been utilized in image processing research since 1973 but has faced criticism for contributing to a sense of exclusion among women in the field.

In an email sent to members, Terry Benzel, the Vice President of Technical & Conference Activities at the IEEE Computer Society, stated, “IEEE’s diversity statement and supporting policies such as the IEEE Code of Ethics speak to IEEE’s commitment to promoting an including and equitable culture that welcomes all. In alignment with this culture and with respect to the wishes of the subject of the image, Lena Forsén, IEEE will no longer accept submitted papers which include the ‘Lena image.'”

Originally appearing as a 512×512-pixel test image in the December 1972 issue of Playboy Magazine, the uncropped version served as the centerfold picture. The use of the Lenna image in image processing began around June or July 1973, when Alexander Sawchuck, an assistant professor, and a graduate student at the University of Southern California Signal and Image Processing Institute scanned a square portion of the centerfold image using a primitive drum scanner, excluding nudity. This scan was initially done for a colleague’s conference paper, subsequently leading to widespread adoption of the image by others in the field.

Throughout the 1970s, 80s, and 90s, the image gained traction in various papers, drawing the attention of Playboy, though the company chose to overlook copyright violations. In 1997, Playboy facilitated the location of Forsén, who made an appearance at the 50th Annual Conference of the Society for Imaging Science and Technology, signing autographs for admirers. “They must be so tired of me … looking at the same picture for all these years!” she quipped at the time. Playboy’s Vice President of new media, Eileen Kent, told Wired, “We decided we should exploit this, because it is a phenomenon.”

The image, featuring Forsén’s visage and a bare shoulder adorned with a hat sporting a purple feather, reportedly served as an excellent test subject for early digital image technology due to its high contrast and intricate detail. However, it also presented a sexually suggestive portrayal of an attractive woman. Its persistent use by men in the computing domain has faced critique over the years, particularly from female scientists and engineers. They argue that the image, especially its association with the Playboy brand, objectifies women and fosters an academic environment where they feel unwelcome.

In response to longstanding criticism, dating back to at least 1996, the journal Nature took the step to prohibit the use of the Lena image in paper submissions in 2018.

According to the comp.compression Usenet newsgroup FAQ document, in 1988, a Swedish publication approached Forsén to inquire about her thoughts on her image being used in computer science, to which she reportedly reacted with amusement. However, in a 2019 Wired article by Linda Kinstler, Forsén expressed no resentment toward the image but voiced regret over not being fairly compensated initially. “I’m really proud of that picture,” she told Kinstler at the time.

However, it appears Forsén has since changed her stance. In 2019, Creatable and Code Like a Girl produced an advertising documentary titled “Losing Lena” as part of a campaign aimed at eliminating the use of the Lena image in technology and image processing fields. In a press release for the campaign and film, Forsén is quoted as saying, “I retired from modelling a long time ago. It’s time I retired from tech, too. We can make a simple change today that creates a lasting change for tomorrow. Let’s commit to losing me.”

Relevant articles:

– Playboy image from 1972 gets ban from IEEE computer journals

– Journal publisher bans Playboy centerfold Lena’s image from research papers , NewsBytes, Fri, 29 Mar 2024 09:50:18 GMT

– It’s time to retire Lena from computer science , Pursuit, Fri, 13 Dec 2019 08:00:00 GMT

– The Playboy Centerfold That Helped Create the JPEG , The Atlantic, Tue, 09 Feb 2016 08:00:00 GMT

The IEEE Computer Society announced to its members on W […]

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Celebrating artificial intelligence, big data, and high-performance computing at the University at Buffalo. 

IAD Days (formerly CDSE Days) is a signature annual event hosted by the Institute for Artificial Intelligence and Data Science. The event brings some of the nation's most prominent data science and AI scholars to Buffalo for a week of workshops, lectures, and networking. The initiative increases educational opportunities and employability for students, attracts new graduate students to UB, and boosts research opportunities for aligned faculty members.

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Rachael Hageman Blair.

Rachael Hageman Blair

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Dianna Cichocki.

Dianna Cichocki

Clinical Associate Professor, Department of Management Science and Systems, University at Buffalo

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Dianna Cichocki serves as a Clinical Associate Professor for the School of Management at the University at Buffalo. Her recent course offerings have included, "Statistical Decisions in Management" in the School of Management's Undergraduate Program, "Statistical Foundations in Analytics" in the online MBA and MSBA programs, and "Data Modeling" in the MBA program, and "Communicating with Data" in the School of Engineering's Undergraduate Program. Beyond her teaching commitments, Dianna actively engages in workshops and presentations at local, state, and national levels. These sessions focus on integrating technology into statistical practices and advocating for effective data visualization methods. Moreover, she has led multiple industry training sessions aimed at bolstering managerial expertise across different organizational tiers.

Sai Vikneshwar Mani Jayaraman.

Sai Vikneshwar Mani Jayaraman

 Software Engineer, AWS Redshift

Read Jayaraman's Bio

Sai is a Software Engineer at AWS Redshift. He is interested in anything and everything about databases. Not so long ago, he finished his PhD from UB under the wise guidance of Atri Rudra. In the past, he has worked on Codes for Distributed Storage (Intern, Microsoft Research), Ads Quality Infra (Intern, Google) and Product Support (Engineer, Microsoft). His work has been published in Principles of Database Systems (PODS) and IEEE Transactions on Information Theory. In a previous avatar, he trained teams for ACM-ICPC (World Finals 2013, 2014).

Ryan A. McPherson.

Ryan A. McPherson

Chief Sustainability Officer, Office of Sustainability, University at Buffalo

Read McPherson's Bio

As UB’s inaugural chief sustainability officer since 2011, Ryan McPherson works to create a culture of innovative and collaborative sustainability at UB and implements strategies to help position the university as a sustainability leader in the community, state and nation, as well as across higher education. Among his chief priorities has been setting 10 key strategies to implement within the next decade as part of the university’s climate action plan. He also has worked to integrate the Sustainable Development Goals across campus and New York as part of the broader work to create the next generation of change agents who are building the future we seek.  

Under McPherson’s oversight, UB has already reduced its carbon footprint by 35% and been recognized as a national model for climate action by Vice President Harris, received the Green Power Leadership Award from the US Environmental Protection Agency, won the New York State Department of Environmental Excellence Award, and rated #1 in the world by the Times Higher Education Impact Assessment in taking urgent action to combat climate change. 

Prior to this role, Ryan was the Associate Vice President for Government & Community Relations where he successfully led a multi-year New York State effort that resulted in the enactment of the most comprehensive higher education in the previous two decades.  He is also very active in the community and sits on numerous boards including the Nature Conservancy (New York), the Western New York Sustainable Business Roundtable, and Gobike Buffalo.  Mr. McPherson is also an adjunct faculty member at the University at Buffalo School of Management.  Ryan received his B.A. in political science from the University of New Hampshire and graduated magna cum laude from the University at Buffalo Law School with a concentration in environmental law.  

Ryan enjoys trail running through nature (and specifically mountains) and spending time with his wife and two near adult children as they work to instill a love of nature and advance all things biophilia. 

Jeffrey Miecznikowski.

Jeffrey Miecznikowski

Associate Professor, Department of Biostatistics, University at Buffalo

Read Miecznikowski's Bio

Jeffrey C. Miecznikowski (“Mesh-KNEE-cow-ski”) received his Ph.D. in Statistics from Carnegie Mellon University in 2006. In 2006, he started as an Assistant Professor in the Department of Biostatistics at the State University of New York at Buffalo (UB) and received tenure in 2012 with appointment to Associate Professor. He has previously served as the Associate Dean of Faculty Affairs and Diversity and as the interim Chair of Biostatistics at UB’s School of Public Health and Health Professions. He has 75 published peer-reviewed articles in statistical journals and applied interdisciplinary journals and is currently an associate editor for the Journal of Applied Statistics and Frontiers in Genetics.

Carolyn Penstein Rose.

Carolyn Penstein Rose

Professor, School of Computer Science, Carnegie Mellon University

Read Rose's Bio

Dr. Carolyn Rosé is a Professor of Language Technologies and Human-Computer Interaction in the School of Computer Science at Carnegie Mellon, and Program Director for the Masters of Computational Data Science Program. Her research program focuses on computational modeling of discourse to enable scientific understanding the social and pragmatic nature of conversational interaction of all forms, and using this understanding to build intelligent computational systems for improving collaborative interactions. She is best known for her work on dynamic support of collaborative learning using intelligent conversational agents in online, face-to-face, and hybrid settings, triggered through real time analysis of conversational interactions. Her research group’s highly interdisciplinary work, published in over 300 peer reviewed publications, is represented in the top venues of 5 fields: namely, Language Technologies, Learning Sciences, Cognitive Science, Educational Technology, and Human-Computer Interaction, with awards in 4 of these fields. She is a Past President and Inaugural Fellow of the International Society of the Learning Sciences, Senior member of IEEE, Founding Chair of the International Alliance to Advance Learning in the Digital Era, and Executive Editor (formerly Co-Editor-in-Chief) of the International Journal of Computer-Supported Collaborative Learning. She also serves as a 2020-2021 AAAS Leshner Leadership Institute Fellow for Public Engagement with Science, with a focus on public engagement with Artificial Intelligence.

Jinjun Xiong.

Jinjun Xiong

SUNY Empire Innovation Professor, Department of Computer Science and Engineering, and Director, Institute for Artificial Intelligence and Data Science, University at Buffalo

Read Xiong's Bio

Dr. Jinjun Xiong is an Empire Innovation Professor with the Department of Computer Science & Engineering, University at Buffalo (UB) . He received his Ph.D. degree in 2006 from University of California, Los Angeles (UCLA) with an Outstanding Ph.D. Award, his M.S. degree from University of Wisconsin, Madison in 2002, and his M.S. and B.S. degrees from Tsinghua University in 2000 and 1998, respectively.

Before joining UB in 2021, Dr. Xiong was Program Director and Senior Research Scientist at IBM T.J. Watson Research Center, Yorktown Heights, NY.  He co-founded and co-directed the IBM-Illinois Center for Cognitive Computing Systems Research with Prof. Wen-mei Hwu. Under their leadership, the C3SR center has expanded from the early days' eight faculty members in 2016 to close to 40 faculty members in 2021. The success of the C3SR center also led to the creation of the new IBM-Illinois Discovery Accelerator Institute, a joint $200-million research investment between IBM and UIUC. Dr. Xiong also co-founded the IBM Smarter Energy Research Institute and led a number of enterprise-scale collaborations with world-wide electric utility companies to address sustainability issues with renewable integration. 

Dr. Xiong's recent research interests are on across-stack AI systems and solutions research, including Innovative AI applications, in particular on education and sustainability, Novel AI algorithms, in particular on computer vision and natural language processing, Productivity tooling for AI development, in particular on software engineering, compilers, and operating systems, and

AI accelerators and computer architectures for edge computing and hybrid clouds, such as  GPUs, and FPGAs.  

He has published more than 150 peer-reviewed papers in top AI conferences and systems conferences. His publication has won seven Best Paper Awards and eight Nominations for Best Paper Awards. Dr. Xiong also won top awards from various international competitions, including the recent Championship Award for the IEEE GraphChallenge on accelerating sparse neural networks, and the Championship Awards for the DAC'19 Systems Design Contest on designing an object detection neural network for both edge FPGA track and the edge GPU track. Many of his research results have been adopted in commercial enterprise-scale products and tools. 

Mohammad Zia.

Mohammad Zia

Systems Architect, Roswell Park Comprehensive Cancer Center

Read Zia's Bio

Mohammad earned his PhD from Rutgers, the State University of New Jersey in Biomedical Engineering. He now works as a systems architect at Roswell Park Comprehensive Cancer Center, specializing in accelerating data-driven research through his expertise in full-stack development. Mohammad also serves as an adjunct lecturer at the University at Buffalo, where he passionately imparts his knowledge of Python and databases to aspiring data scientists.

Ziliang Zong.

Ziliang Zong

 Professor, Department of Computer Science, Texas State University

Read Zong's Bio

Dr. Ziliang Zong is a Professor of the Computer Science Department at Texas State University. He is a passionate researcher, teacher, and practitioner of sustainable computing. He published over 100 papers in green AI, green cloud, green software engineering, energy efficient HPC, and green computing education. He is a general member and champion speaker of the Green Software Foundation, an Associate Editor of the Sustainable Computing Journal, and Director of the Energy Efficient Computing and Systems Laboratory at Texas State University.

Abstracts will be linked to each presentation topic below. Click on the speaker's name to learn more about each presenter. Jump to:  Wednesday    Thursday    Friday

Wednesday, April 17

Thursday, april 18, friday, april 19, abstracts & session details, democratization responsible artificial intelligence.

Artificial intelligence (AI) is driving discovery, innovation, and economic growth, and has the potential to transform science and society. However, realizing this  positive and transformative potential of AI requires that AI research and development (R&D) progresses responsibly, i.e., in a way that protects privacy, civil rights, and civil liberties, and promotes principles of fairness, accountability, transparency, and equity. In this talk, I will explore the importance of democratizing AI R&D for achieving the goal of responsible AI and the resulting imperative of democratizing access to advanced cyberinfrastructure. I will then discuss recent efforts in government and academia aimed at achieving these goals. Finally, it introduces the Responsible AI Initiative at the University of Utah.

Advancing Beyond Scikit-learn and Jupyter Notebook

Break free from the limitations of standard machine learning practices by exploring advanced tools in this workshop led by Mohammad. Participants will delve into supplementary tools and platforms for engineering features, tracking model experiments, deploying models, and detecting data shifts.

Introduction to Bayesian Networks with Applications in R

Probabilistic Graphical Models (PGMs) are used broadly across many fields to model the connectivity relationships between entities in a network. This workshop introduces Bayesian Networks, a special class of directed and acyclic PGMs. BNs are “expert systems” widely used for inference and prediction. Methods for parameter and structural learning will be discussed and implemented using the R programming language. Probabilistic reasoning will be described for making predictions within these networks. In the second part of the workshop, attendees will have a “hands-on” experience with network construction, inference, and visualization using the R programming language. Programming experience is not required. This workshop serves as a preview for a 1-credit course in the IAD’s ‘summer stackable’ graduate elective series. 

Beyond Data Dumps: Using Charts to Tell Stories

The gap between data analysis and effective communication of results keeps growing. This two-hour session provides the framework for bridging the gap by turning basic charts into compelling stories. Being able to analyze data and tell stories with the results is key to transforming data into information that can be used to drive better decision-making.

We will create visualizations that accurately, effectively, and efficiently communicate a story rather than a “data dump.”

Challenges and Opportunities of Sustainable AI at All Scopes

In recent years, the proliferation of AI technologies has led to significant advancements across various sectors, but concurrently, it has raised concerns about its environmental impact. This talk explores the challenges and opportunities associated with fostering sustainable AI practices across all scopes of emissions. Beginning with an overview of Scope 1 emissions, we delve into the direct environmental footprint of AI development and deployment. Moving to Scope 2 emissions, we examine the indirect environmental impacts arising from the electricity consumption of AI-related operations. Finally, we discuss the complexities of Scope 3 emissions, encompassing the entire lifecycle of AI technologies. By understanding and addressing sustainability challenges at all scopes, we can identify opportunities for implementing strategies to minimize environmental harm while maximizing the societal benefits of AI innovation. This research talk highlights the importance of holistic approaches to achieve sustainable AI development and underscores the urgent need for collaboration among stakeholders to mitigate environmental impacts across the AI ecosystem.

Coding From Theory to Practice

Typically, we are taught a lot of programming in school. However, when we go to industry, does the kind of programming we know remain the same? What constitutes good code? Tune in to the talk for answers.

Exploring the Flexibility of Linear Regression Models

Linear regression models are a mainstay in the statistician’s toolbox for understanding the relationships between variables. Their popularity is due to their simplicity, flexibility, and ease in computation and interpretation. In this workshop, we explore linear regression models starting from the simplest setting with a focus on the general paradigm of model assumptions and associated parameter estimation via maximum likelihood. We then explore different linear regression models and assumptions, ultimately, revealing the flexibility of the linear regression modeling approach. 

Social Analytics and Dynamic Support for Collaborative Learning in the Age of Large Language Models

This talk is built on a decade and a half of research into supporting social interaction in online communities, exploring what design principles we have empirically validated, what technological advances have produced novel interventions aligned with those principles, and what questions we still need to answer. In particular, this talk highlights social analytics as an area of Artificial Intelligence that plays a role in supporting education that has featured in movements towards large scale learning opportunities, such as promised in Massive Open Online Courses (MOOCs) as well as in more traditional Computer-Supported Collaborative Learning environments. Recent advances in Generative AI (GenAI) and Large Language Models (LLMs) have enhanced AI capabilities for the evaluation of multimodal student input and real-time feedback, which has provoked intensive exploration of the space of application possibilities. This technology opens up more options for adapting the specific content of reflection triggers from specific details of the students’ work and discussion in context. This talk will discuss recent advances in support of collaboration using GenAI and LLMs, with a particular focus on two recent classroom studies investigating LLM-based support for reflection and learning during collaborative software development.

AI Literacy x Sustainability Literacy

Ryan mcpherson.

The 21st century is punctuated by two themes that shape the planet’s discourse - AI and Sustainability. This panel explores the closely tied yet, parallel initiatives in these fields. Experts in Sustainability and Artificial intelligence discuss, debate, and dissect the role of AI in Sustainability Initiatives, the sustainable development of AI, and the role that each can play in shaping the other’s future.

To equip the planet’s future with a population well-informed on the criticality of AI and sustainability, the panel emphasizes on and shapes the best practices in AI Literacy, Sustainability Literacy, and the significant overlap between the two.

On-Device AI to Better Mobile and Implantable Devices in Healthcare

The increasing prevalence of chronic diseases, an aging population, and a shortage of health care professionals have prompted the widespread adoption of mobile and implantable devices to effectively manage various health conditions. In recent years, there is growing interest to leverage the rapid advances in artificial intelligence (AI) to enhance the performance of these devices, resulting in better patient outcomes, reduced health care costs, and improved patient autonomy. Due to privacy, security, and safety considerations, inferences must often be done on the edge, with limited hardware resources. This is compounded by inter-patient and intra-patient variability, heavy dependence on medical domain knowledge, and lack of diversified training data. In this talk, we will demonstrate how techniques such as hardware and neural architecture co-design can transform the landscape of mobile and implantable devices. Additionally, we will showcase the world's first smart Implantable Cardioverter Defibrillator (ICD) design enabled by our research.

As part of IAD Days, CDSE students will be expected to participate in a poster session at the reception on Wednesday, April 17 from 3:00-4:00 pm. Poster abstracts should be submitted by Monday, April 8 at 5:00 pm.

IAD will cover the cost of poster printing. When you submit an abstract, you will also be eligible to participate in the student talk competition. IAD will choose the top three abstracts that have been submitted to additionally present their work in the form of a 10-minute research talk on Wednesday, March 29th from 3:30-4:00 pm. Students selected for talks will be notified by March 17th.

Posters must be submitted by Monday, April 8  to ensure they are printed in time for IAD Days. Students can submit both their poster files and abstracts via the link below.

IAD Days Poster Session and Networking Event.

Registration is now closed.  If you have any questions about IAD Days, email us at  [email protected] .

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image processing —

Playboy image from 1972 gets ban from ieee computer journals, use of "lenna" image in computer image processing research stretches back to the 1970s..

Benj Edwards - Mar 29, 2024 9:16 pm UTC

Playboy image from 1972 gets ban from IEEE computer journals

On Wednesday, the IEEE Computer Society announced to members that, after April 1, it would no longer accept papers that include a frequently used image of a 1972 Playboy model named Lena Forsén. The so-called " Lenna image ," (Forsén added an extra "n" to her name in her Playboy appearance to aid pronunciation) has been used in image processing research since 1973 and has attracted criticism for making some women feel unwelcome in the field.

Further Reading

In an email from the IEEE Computer Society sent to members on Wednesday, Technical & Conference Activities Vice President Terry Benzel wrote , "IEEE's diversity statement and supporting policies such as the IEEE Code of Ethics speak to IEEE's commitment to promoting an including and equitable culture that welcomes all. In alignment with this culture and with respect to the wishes of the subject of the image, Lena Forsén, IEEE will no longer accept submitted papers which include the 'Lena image.'"

An uncropped version of the 512×512-pixel test image originally appeared as the centerfold picture for the December 1972 issue of Playboy Magazine. Usage of the Lenna image in image processing began in June or July 1973 when an assistant professor named Alexander Sawchuck and a graduate student at the University of Southern California Signal and Image Processing Institute scanned a square portion of the centerfold image with a primitive drum scanner, omitting nudity present in the original image. They scanned it for a colleague's conference paper, and after that, others began to use the image as well.

The original 512×512

The image's use spread in other papers throughout the 1970s, '80s, and '90s , and it caught Playboy's attention, but the company decided to overlook the copyright violations. In 1997, Playboy helped track down Forsén, who appeared at the 50th Annual Conference of the Society for Imaging Science in Technology, signing autographs for fans. "They must be so tired of me... looking at the same picture for all these years!" she said at the time. VP of new media at Playboy Eileen Kent told Wired , "We decided we should exploit this, because it is a phenomenon."

The image, which features Forsén's face and bare shoulder as she wears a hat with a purple feather, was reportedly ideal for testing image processing systems in the early years of digital image technology due to its high contrast and varied detail. It is also a sexually suggestive photo of an attractive woman, and its use by men in the computer field has garnered criticism over the decades, especially from female scientists and engineers who felt that the image (especially related to its association with the Playboy brand) objectified women and created an academic climate where they did not feel entirely welcome.

Due to some of this criticism, which dates back to at least 1996 , the journal Nature banned the use of the Lena image in paper submissions in 2018.

The comp.compression Usenet newsgroup FAQ document claims that in 1988, a Swedish publication asked Forsén if she minded her image being used in computer science, and she was reportedly pleasantly amused. In a 2019 Wired article , Linda Kinstler wrote that Forsén did not harbor resentment about the image, but she regretted that she wasn't paid better for it originally. "I’m really proud of that picture," she told Kinstler at the time.

Since then, Forsén has apparently changed her mind. In 2019, Creatable and Code Like a Girl created an advertising documentary titled Losing Lena , which was part of a promotional campaign aimed at removing the Lena image from use in tech and the image processing field. In a press release for the campaign and film, Forsén is quoted as saying, "I retired from modelling a long time ago. It’s time I retired from tech, too. We can make a simple change today that creates a lasting change for tomorrow. Let’s commit to losing me."

It seems like that commitment is now being granted. The ban in IEEE publications, which have been historically important journals for computer imaging development, will likely further set a precedent toward removing the Lenna image from common use. In the email, IEEE's Benzel recommended wider sensitivity about the issue, writing, "In order to raise awareness of and increase author compliance with this new policy, program committee members and reviewers should look for inclusion of this image, and if present, should ask authors to replace the Lena image with an alternative."

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