vhdl procedure signal assignment

How to use a procedure in a process in VHDL

It is possible to drive external signals from a procedure. As long as the signal is within the scope of the procedure, it can be accessed for reading or writing, even if it isn’t listed in the parameter list.

Procedures that are declared in the declarative region of the architecture, cannot drive any external signals. This is simply because there are no signals in its scope at compile time. A procedure declared within a process, on the other hand, will have access to all of the signals that the process can see.

This blog post is part of the Basic VHDL Tutorials series.

Such procedures can be used for decluttering algorithms in processes where the same operations occur several times. We could use a normal procedure where all the inputs and outputs are assigned to local signals when you call it, but that is not the point. By omitting the input and output signals from the procedure call, we must type less, and more importantly, we make the code more readable.

Imagine a process implementing a complex communication protocol. It would be a lot easier to understand the execution flow of the main algorithm if some operations were replaced by procedure calls like RequestToSend() or SendAutorizationHeader() . You would know what those lines did just be looking at the procedure names.

In the previous tutorial , we simplified our finite-state machine (FSM) code by using an impure function. We were driving the Counter signal from the impure function, and we used the return value to determine when to change state. But what if we want to move the assignment of the State signal into the function as well, and ignore the return value?

It’s not possible to call a function without assigning the return value to something in VHDL. If we try to do so, ModelSim will produce the compile error:  No feasible entries for subprogram “CounterExpired” .

Instead, we can use a procedure for this. A procedure declared within a process can access any signal within the scope of that process. This is similar to the impure function, but since it’s a procedure, there is no return value.

In this video tutorial we will simplify the FSM code by using a procedure declared in a process:

The final code for the Procedure in Process testbench :

The final code for the Traffic Lights module :

The waveform after we entered the run 5 min command in the ModelSim console:

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We haven’t changed the behavior of the module, and we can see that the waveform is unchanged.

Compared to the code from the tutorial where we initially created the traffic lights module , the FSM code is much more readable now. You can easily follow the algorithm that it implements by reading the code. Having the timer and state change logic in a single procedure is beneficial because it ensures that it’s implemented equally everywhere it’s used.

• A procedure declared in a process can access any signal within the scope of that process
• Procedures within processes can be used for improving code readability

I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.

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Thank you for this blog post! While writing procedure why did you not indicate “in”- “out”s and “signals”-“constant”s, like you did in the procedure video? Is it about “procedure” being in “progress”?

That’s a good observation and a great question!

Let’s see what the VHDL standard has to say: “If no object class is explicitly given, constant is assumed.”

And a constant always has “in” mode. Therefore, our parameter list is implicitly the same as this:

Great lesson as always. Just a contribution: I think there is a error in the text where you say “This is similar to the impure process”, you actually mean “impure function”, right?

Thanks, Rafael. You are entirely correct. I’ve changed the erroneous text to “impure function”. ?

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Procedure Statement – VHDL Example

Procedures are part of a group of structures called subprograms. Procedures are small sections of code that perform an operation that is reused throughout your code. This serves to cleanup code as well as allow for reusability.

Procedures can take inputs and generate outputs. They can generally be more complicated than functions . It is not required to pass any signals to a procedure. In the example below there is a procedure p_INCREMENT_SLV whose purpose is to increment a standard logic vector by 1 and generate a signal with the result.

One additional note about using wait statements: Wait statements CAN be used in a procedure, as long as the process that calls the procedure does not have a sensitivity list. In the example below the procedure has a 1 ns wait statement to demonstrate this. This makes procedures useful for creating testbench code.

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Signal Assignments in VHDL: with/select, when/else and case

Sometimes, there is more than one way to do something in VHDL. OK, most of the time , you can do things in many ways in VHDL. Let’s look at the situation where you want to assign different values to a signal, based on the value of another signal.

With / Select

The most specific way to do this is with as selected signal assignment. Based on several possible values of a , you assign a value to b . No redundancy in the code here. The official name for this VHDL with/select assignment is the selected signal assignment .

When / Else Assignment

The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check ( a = ) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that’s used in the selected signal assignment was a comma. In the conditional signal assignment, you need the else keyword. More code for the same functionality. Official name for this VHDL when/else assignment is the conditional signal assignment

Combinational Process with Case Statement

The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That’s not a big effort, but while I was drafting this, I had put b in the sensitivity list instead of a . Easy to make a small misstake. You also need to specify what happens in the other cases. Of course, you could do the same thing with a bunch of IF-statements, either consecutive or nested, but a case statement looks so much nicer.

While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.

Hard to remember

The problem with the selected and conditional signal assignments is that there is no logic in their syntax. The meaning is almost identical, but the syntax is just different enough to throw you off. I know many engineers who permanenty have a copy of the Doulos Golden Reference Guide to VHDL lying on their desks. Which is good for Doulos, because their name gets mentioned all the time. But most people just memorize one way of getting the job done and stick with it.

• VHDL Pragmas (blog post)
• Records in VHDL: Initialization and Constraining unconstrained fields (blog post)
• Finite State Machine (FSM) encoding in VHDL: binary, one-hot, and others (blog post)
• "Use" and "Library" in VHDL (blog post)
• The scope of VHDL use clauses and VHDL library clauses (blog post)

In VHDL -93, any signal assignment statement may have an optional label: