systemverilog assignment operators

Types, Operator, and Expressions

Like ordinary software programming languages, SystemVerilog allows designers manipulate different types and data objects when modeling the hardware. Although bears much similarity to languages such as C/C++ (in fact SystemVerilog is influenced by them), SystemVerilog is a language to model hardware, which has different semantics than software programming models. This chapter explores the type system and associated operators in SystemVerilog.

2.1 Data Types

SystemVerilog uses the terminology of data type and data objects to distinguish between objects and its data type. As specified in the language specification, a data type is a set of values and a set of operations that can be performed on those values. A data object is a named entity that has a data value and a data type associated with it.

2.1.1 4-State Values

One major distinction between SystemVerilog and other software programming languages is that the value set in SystemVerilog consists of the following four basic values:

• 0 : represents a logic zero or false condition
• 1 : represents a logic one or true condition
• x : represents an unknown value
• z : represents a high-impedance state.

Values 0 and 1 serve the same purpose as in languages such as C/C++, but x and z are hardware specific. High-impedance value z typically implies a physically disconnected state, i.e. an infinitely high resistance. It commonly appears in designs where a pin used as a bi-directional bus, e.g. tri-state. Unknown value x means the system is able to determine the value, which may happen in various condition. One common situation for x to appear in simulation is usage of uninitialized memory cells. Another common scenario is low-power designs where some part of circuit is “shut-down”, i.e. no supply voltage. Any signal coming out from the shut-down region will be x. Keep in mind that x can propagate through your circuit if not taken care of, since any logic operation on unknown values results in unknown values.

Notice that the truth table for 4-state values are slightly different than the normal 2-state values. Any 4-state value OR with 1 is 1 , any 4-state value AND with 0 is 0, and any 4-state value XOR with x is x . This can be useful when dealing with x-prorogation.

Data types that only use 0 or 1 have 2-state values.

2.1.2 Basic data types

logic is the most commonly used basic data types in SystemVerilog. logic signal has 4-state values. It can either represent a combinational signal or a sequential signal, since the downstream tools such simulator and synthesis tools will determine whether to instantiate a flip-flop based on the usage. A rule of thumb is that any signals in your synthesizable design should be declared as logic (a few exceptions apply, which will be discussed). This is to ensure that the simulator and synthesis tool agree with each other, avoiding critical bugs that can only been discovered through gate-level simulation or even post-silicon tests. For instance, if a signal is declared as 2-state value, the simulator will happily compute with 0 and 1s. However, since the actual silicon has z and x values, we will see a discrepancy after the synthesis, which leads to a potential bug.

By default, a signal declared as logic only has one bit value. To declare a multi-bit signal, we can do logic[15:0] a , which declares a 16-bit signal. Notice that we can also do logic[0:15] a . The difference is bit-ordering, similar to endianness for byte-ordering. Typically bit-ordering follows the same endianness as the byte order. It is highly recommend to use a consist bit-ordering throughout the design to avoid potential bugs. In this book we will use big-endian and high:low bit-ordering.

By default, every declared variable is unsigned. To declare a signed variable, use signed keyword such as logic signed [15:0] a . Although SystemVerilog allows you to mix signed variable with unsigned, similar to C/C++, it leaves a potential bug that cannot be caught by the compiler (some tools may produce a warning), we shall never mix signed and unsigned arithmetics and any assumption about the how the automatic conversion work is grounded for future errors that is difficult to debug.

To declare an array, we can add extra dimension to the “left”, such as logic[3:0][15:0] a , which declares 4 16-bit logics. We can adding arbitrary more dimensions as well. The array created by such approached is called packed array. To access the first 16-bit logic , we can do a[0] . Notice that we can also slice out a sub-array, such as a[1:0] , which gives as the first two values.

Notice that we can also do logic[15:0] a[3:0] , which is called unpacked array. Although unpacked array has advantage over packed array such as giving simulator more flexibility to allocate arrays since they do not need to be contiguous, because of that, we cannot slice a sub-array, nor can we bulk assign values. Again, choosing which representation depends on the project style, as long as it is consistent throughout the entire project. In this book we will use packed array.

2.1.2.1 2-state Variables

SystemVerilog also defines 2-state types, typically used for test benches or functional models that are more high-level. Unlike C, these data types has pre-defined widths, as show in Table 2 .

2.1.3 Enumeration

SystemVerilog defines enumerations as a set of integral named constants, similar to that of C/C++. Enumeration need to be declared with a type with the default type be int . Since int is unwelcoming in synthesizable RTL, we shall always use logic data types. An example of enumeration is shown below:

Here are some rules regarding the name and integral values of enumeration:

Values in enum can be integers and increment from an initial value of 0. This, however, can be overridden, as shown below. In this case, STATE2 will be 2 and STATE3 will be 3.

• Both the enumeration names and their integer values shall be unique. This can be combined with the first rule.

The integer values in enumerate will be casted to their corresponding type. An overflow will be treated as an error

Enumeration are strongly typed. Although directly assigning integer to enumerate variables will trigger an automatic cast, we highly recommend to use explicit cast.

There are several helper functions with enumerated types:

first() : returns the value of the first member of the enumeration.

• last() : returns the value of the last member of the enumeration.

next(int unsigned N = 1) : returns N th next enumeration stating from the current value.

prev(int unsigned N = 1) : returns N th previous enumeration value starting from the current value.

Notice that next() and prev() are type-safe ways to increment enumeration values, which is highly recommend to use compared to simply addition followed by mod.

2.1.4 Struct

To represent data in a more meaningful way, SystemVerilog allows users to define a struct similar to C/C++. The members of a struct can be any data type, thus nesting struct is allowed. Since struct represents an aggregated values, similar to array, we have the concept of packed and unpacked struct. By default, without packed keyword, the struct is unpacked. Again we will use packed struct in this book. Here is an example to define an instruction type;

2.1.5 User-Defined Types

Like C, SystemVerilog allows complex data types to be aliased to a new type using the keyword typedef to make the code more readable. The syntax is similar to that of C as well:

For instance, to define the state enumeration as a new type, we can do something such as

enum definition is between typedef and state_enum_t . We can then use state_enum_t as a type to declare state variable. Notice that we add suffix _t to indicate that state_enum_t is a user-defined type. This is a useful naming convention that has been adopted in many design style guides and we will follow this convention in the book.

Similar to enum , we can use typedef to give struct a type name and re-use it later.

In the example here we first define data_t and refer to it when defining inst_t . Since we use packed for both struct , we can actually assign the instruction to a 32-bit signal.

We can also use typedef to define other types. For instance, typedef logic[7:0] byte_logic defines a byte_logic as 8-bit logic. We can stack typedef on top of each other. For instance, typedef byte_logic[7:0] int_logic defines int_logic to be a packed array of byte_logic .

2.1.6 Union

Although SystemVerilog offers the union similar to that of C/C++, it introduces a potential type loophole since the union can be updated using a value of one memory type and read as a value of another member type. To avoid this, SystemVerilog introduce a new construct called tagged union. A tagged union stores both the member values and a tag . The tag and value can only be updated together using a type-checked expression, as specified by the SystemVerilog standard. We will focus on tagged union since it offers more type safety and it is an underrated feature introduced by SystemVerilog.

In the example here, we will try to specify RISC-V basic instruction formats. The complete code can be found in 02/tagged_union.sv . Unfortunately, at the time of writing, only the latest vcs supports tagged union feature.

Notice that we use the keyword packed here, which tells the compiler to check the bit-width for each union member to make sure they are match. In most cases we want the same size, hence packed needed. However, in the case where tagged union has unmatched bit-width, the tools need to layout the memory carefully. Readers are encouraged to refer to Section 7.3.2 in the SystemVerilog standard for more details.

In the example, we have explicitly specify the tag for the variable, and the tag value is checked at runtime to ensure the type correctness.

For completeness, we cover the ordinary union here, which shares the same semantics as that of C/C++.

In this example, we can assign value to raw_value and then read out appropriate values from inst .

2.1.7 Non-Synthesizable Data Types

When modeling high-level logic designs, such as functional model used for test benches, we can use non-synthesizable data types to reduce the amount of work. For instance, SystemVerilog offers data type real and shortreal the same way as double and float in C, respectively, which conforms to IEEE Standard 754. This can be useful when developing models that needs floating point. HOwever, please keep in mind that if you want to use floating points in your synthesizable design, you have to either use vendor provided IPs, or implement your own. The former approach is recommended, since they have been thoroughly verified and optimized for various design metrics.

Another data-type non-synthesizable data type is string . string in SystemVerilog is close to that of Python where the space allocation is fixed. However, although string itself is not synthesizable, logics can be assigned directly from string literals. The tools will automatically convert the string literal into bytes based on the ASCII table behind the scene. Please keep this in mind when using string literals in your synthesizable design, as shown in the code usage in the code blow. Notice that since the string literal is represented as logic, we can display it in both string and number format, whereas the the string data type cannot.

One thing to keep in mind when using string literal assigned to numeric types such as logic : if the string length smaller than the bit width of the variable, 0 padding happens. SystemVerilog will pad 0 to the left, which can be a potential problem as normal software programming languages do not have such behavior.

2.1.7.1 Other Data Types

There are other data types in SystemVerilog we have not covered so far, such as event and chandle . We will cover chandle later in DPI, which is a data type used for foreign language pointers.

2.1.8 Type Casting

Many types in SystemVerilog are strongly typed, meaning a wrong type assignment will trigger either a compiler warning or error, such as directly assigning logic values to enum variables. Unfortunately its predecessor Verilog is weak-typed and SystemVerilog inherits all its shortcomings, such as mixing with signed and unsigned assignments. To make the code less error-prone, it is recommended to stick with explicit casting whenever there is a type mismatch, rather than relying on the language’s default type conversions.

A data type can be casted into another using the cast ' operation. The general syntax is

For instance, suppose we have a enum type state_enum_t defined earlier, and we want to directly assign a logic to it (not recommended but in some cases it is necessary), we can cast the logic variable to the enum type we want, as shown below.

To cast an unsigned number to signed, we can use signed'() , and unsigned ()` to cast signed to unsigned numbers.

2.1.9 Variable scopes and lifetime

Variables in SystemVerilog can have different lifetime depends on where and how they are defined. We will discuss more in details in the next chapter when we discuss various scopes.

2.2 Operator and Expressions

2.2.1 numeric literals.

Numeric literals in SystemVerilog can be specified in decimal, hexadecimal, octal, or binary format. The general syntax to specify a numeric literals is shown below (taken from SystemVerilog standard A.8):

By default, any numeric literal without any additional specification is in unsigned decimal base, such as 42 . To specify its size, we need ' operator to separate the size and value, such as 16'42 , which specifies a 16-bit value. We can also specify different base using letters such as d , b , and h . For instance, 16'h10 specifies a 16-bit value 0x10. If we want the numbers to be signed, we can use s after the ' , such as -16's10 , which specifies a 16-bit signed value -10. When representing non-decimal numbers, especially binary, we can use _ as a delimiter to annotate bytes. For instance, to represent 123 in a 8-bit unsigned number in binary, we can use 8'b0111_1011 , where we put _ for every 4 bits. One thing to keep in mind that although SystemVerilog allows you to drop the size, called unsized number, certain rule apply:

• The number of bits that mark up the unsized number shall lbe at least 32. This implies that if you assigned an unsized number to a variable with fewer than 32 bits, truncation will happen.
• If unsized number is used in an expression, the other values has higher number of bit width, the unsized number will be extended with respect to the highest bit, including x and z .

As a result, we only recommend to use unsized number such as 0, where the extension and truncation do not affect the actual value. For other occasions the size is recommended since it helps linters to catch size mismatch.

2.2.2 Struct and Array Literals

Although we can set the struct members individually when initializing the struct variable, SystemVerilog provides a concise way to do so. Suppose we have a struct and a variable defined as

Instead of assigning values to a and b individually, we can use the structure assignment patterns by using '{} :

This assignment pattern also works for an array of structures, which is similar to that of C++:

Array literals assignment is the same as struct literal, where each item in the array can be specified using '{} syntax. Notice that we can use replication operator {{}} to make the code more readable.

2.2.3 Operators

SystemVerilog has a rich set of operators similar to that of C/C++ with enhancement to deal with bit vectors. The complete operators and data types is listed in Table 3 , which is taken from Table 11-1 from the SystemVerilog standard.

Most of the operators have the same semantics as C/C++. However, there are several operators to which we need to pay attention:

• Unary logical reduction operators. This set of operators forms a reduction tree on every bit of the variable. For instance, if we have a 4-bit variable logic [3:0] a = 'b0010 . |a is equivalent to to a[0] | a[1] | a[2] | a[3] , which is 1, and &a yields 0.
• Concatenation operator {} allows multiple variable append to each other, resulting in a wider variable. Suppose we have 2 variables logic [1:0] a = 'b11 and logic [3:0] b = 'b0010 , {a, b} yields 'b110010 . We can concat as many as variable as we need. SystemVerilog also offers a shorthand to repetitively concatenate variables together. For instance, {4{'b10}} yields 'b10101010 .
• The difference between == and === lies in 4-state value comparison: == only compares 2-state and === compares 4-state. Suppose we have a = 1'bx and c = a == 1'bx , where a and c are 1-bit logic . Because == only compares 2-state, c is x . If c is defined as c = a === 1'bx , c will be 1.
• Shifter has two forms: arithmetic and logic shifters. Arithmetic shifters does signed extension when shift right where as logic shifters always pad zero when shifting. One common gotcha is that even though a variable is declared as signed, if you use >> to shift right, SystemVerilog will not perform signed extension, a behavior different from C! We have seen the actual bug went into silicon before getting caught.

Verilog Assignments

Variable declaration assignment, net declaration assignment, assign deassign, force release.

• Procedural continuous

Legal LHS values

An assignment has two parts - right-hand side (RHS) and left-hand side (LHS) with an equal symbol (=) or a less than-equal symbol (<=) in between.

The RHS can contain any expression that evaluates to a final value while the LHS indicates a net or a variable to which the value in RHS is being assigned.

Procedural Assignment

Procedural assignments occur within procedures such as always , initial , task and functions and are used to place values onto variables. The variable will hold the value until the next assignment to the same variable.

The value will be placed onto the variable when the simulation executes this statement at some point during simulation time. This can be controlled and modified the way we want by the use of control flow statements such as if-else-if , case statement and looping mechanisms.

An initial value can be placed onto a variable at the time of its declaration as shown next. The assignment does not have a duration and holds the value until the next assignment to the same variable happens. Note that variable declaration assignments to an array are not allowed.

If the variable is initialized during declaration and at time 0 in an initial block as shown below, the order of evaluation is not guaranteed, and hence can have either 8'h05 or 8'hee.

Procedural blocks and assignments will be covered in more detail in a later section.

Continuous Assignment

This is used to assign values onto scalar and vector nets and happens whenever there is a change in the RHS. It provides a way to model combinational logic without specifying an interconnection of gates and makes it easier to drive the net with logical expressions.

Whenever b or c changes its value, then the whole expression in RHS will be evaluated and a will be updated with the new value.

This allows us to place a continuous assignment on the same statement that declares the net. Note that because a net can be declared only once, only one declaration assignment is possible for a net.

Procedural Continuous Assignment

• assign ... deassign
• force ... release

This will override all procedural assignments to a variable and is deactivated by using the same signal with deassign . The value of the variable will remain same until the variable gets a new value through a procedural or procedural continuous assignment. The LHS of an assign statement cannot be a bit-select, part-select or an array reference but can be a variable or a concatenation of variables.

These are similar to the assign - deassign statements but can also be applied to nets and variables. The LHS can be a bit-select of a net, part-select of a net, variable or a net but cannot be the reference to an array and bit/part select of a variable. The force statment will override all other assignments made to the variable until it is released using the release keyword.

Continuous Assignment and Combinational Logic in SystemVerilog

In this post, we primarily talk about the concept of continuous assignment in SystemVerilog . We also look at how we can use this in conjunction with the SystemVerilog operators to model basic combinational logic circuits .

However, continuous assignment is a feature which is entirely inherited from verilog so anyone who is already familiar with verilog can skip this post.

There are two main classes of digital circuit which we can model in SystemVerilog – combinational and sequential .

Combinational logic is the simplest of the two, consisting solely of basic logic gates, such as ANDs, ORs and NOTs. When the circuit input changes, the output changes almost immediately (there is a small delay as signals propagate through the circuit).

In contrast, sequential circuits use a clock and require storage elements such as flip flops . As a result, output changes are synchronized to the circuit clock and are not immediate.

In the rest of this post, we talk about the main techniques we can use to design combinational logic circuits in SystemVerilog.

In the next post, we will discuss the techniques we use to  model basic sequential circuits .

Continuous Assignment in SystemVerilog

In verilog based designs, we use continuous assignment to drive data on verilog net types . As a result of this, we use continuous assignment to model combinational logic circuits.

In SystemVerilog, we often use the logic data type rather than the verilog net or reg types. This is because the behavior of the logic type is generally more intuitive than the reg and wire types.

Despite this, we still make use of continuous assignment in SystemVerilog as it provides a convenient way of modelling combinational logic circuits.

We can use continuous assignment with either the logic type or with net types such as wire.

In SystemVerilog, we can actually use two different methods to implement continuous assignment.

The first of these is known as explicit continuous assignment. This is the most commonly used method for continuous assignment in SystemVerilog.

In addition, we can also use implicit continuous assignment, or net declaration assignment as it is also known. This method is less common but it can allow us to write less code.

Let's look at both of these techniques in more detail.

• Explicit Continuous Assignment

We normally use the assign keyword when we want to use continuous assignment in SystemVerilog. This approach is known as explicit continuous assignment.

The SystemVerilog code below shows the general syntax for continuous assignment using the assign keyword.

In this construct, we use the <variable> field to give the name of the signal which we are assigning data to. As we mentioned earlier, we can only use continuous assignment to assign data to net or logic type variables.

The <value> field can be a fixed value or we can create an expression using the SystemVerilog operators we discussed in a previous post.

When we use continuous assignment, the <variable> value changes whenever one of the signals in the <value> field changes state.

The code snippet below shows the most basic example of continuous assignment in SystemVerilog. In this case, whenever the b signal changes states, the value of a is updated so that it is equal to b.

• Net Declaration Assignment

We can also use implicit continuous assignment in our SystemVerilog designs. This approach is also commonly known as net declaration assignment in SystemVerilog.

When we use net declaration assignment, we place a continuous assignment in the statement which declares our signal. This can allow us to reduce the amount of code we have to write.

To use net declaration assignment in SystemVerilog, we use the = symbol to assign a value to a signal when we declare it.

The code snippet below shows the general syntax we use for net declaration assignment.

The variable and value fields have the same function for both explicit continuous assignment and net declaration assignment.

As an example, the SystemVerilog code below shows how we would use net declaration assignment to assign the value of b to signal a.

Modelling Combinational Logic Circuits in SystemVerilog

We use continuous assignment and the SystemVerilog operators to model basic combinational logic circuits in SystemVerilog.

In order to show we would do this, let's look at the very basic example of a three input and gate as shown below.

In order to model this circuit in SystemVerilog, we must use the assign keyword to drive the data on to the and_out output.

We can then use the bit wise and operator (&) to model the behavior of the and gate.

The code snippet below shows how we would model this three input and gate in SystemVerilog.

This example shows how simple it is to design basic combinational logic circuits in SystemVerilog. If we need to change the functionality of the logic gate, we can simply use a different SystemVerilog bit wise operator .

If we need to build a more complex combinational logic circuit, it is also possible for us to use a mixture of different bit wise operators.

To demonstrate this, let's consider the basic circuit shown below as an example.

In order to model this circuit in SystemVerilog, we need to use a mixture of the bit wise and (&) and or (|) operators. The code snippet below shows how we would implement this circuit in SystemVerilog.

Again, this code is relatively straight forward to understand as it makes use of the SystemVerilog bit wise operators which we discussed in the last post.

However, we need to make sure that we use brackets to model more complex logic circuit. Not only does this ensure that the circuit operates properly, it also makes our code easier to read and maintain.

Modelling Multiplexors in SystemVerilog

Multiplexors are another component which are commonly used in combinational logic circuits.

In SystemVerilog, there are a number of ways we can model these components.

One of these methods uses a construct known as an always block which we will discuss in detail in the next post. Therefore, we will not discuss this approach to modelling multiplexors in this post.

However, we will look at the other methods we can use to model multiplexors in the rest of this post.

• SystemVerilog Conditional Operator

As we talked about in a previous post, there is a conditional operator in SystemVerilog . This functions in the same way as the conditional operator in the C programming language.

To use the conditional operator, we write a logical expression before the ? operator which is then evaluated to see if it is true or false.

The output is assigned to one of two values depending on whether the expression is true or false.

The SystemVerilog code below shows the general syntax which the conditional operator uses.

From this example, it is clear how we can create a basic two to one multiplexor using this operator.

However, let's look at the example of a simple 2 to 1 multiplexor as shown in the circuit diagram below.

The code snippet below shows how we would use the conditional operator to model this multiplexor in SystemVerilog.

• Nested Conditional Operators

Although this is not common, we can also write code to build larger multiplexors by nesting conditional operators.

To show how this is done, let's consider a basic 4 to 1 multiplexor as shown in the circuit below.

In order to model this in SystemVerilog using the conditional operator, we treat the multiplexor circuit as if it were a pair of two input multiplexors.

This means one multiplexor will select between inputs A and B whilst the other selects between C and D. Both of these multiplexors use the LSB of the address signal as the address pin.

The SystemVerilog code shown below demonstrates how we would implement this.

To create the full four input multiplexor, we would then need another multiplexor.

This multiplexor then takes the output of the other two multiplexors and uses the MSB of the address signal to select between.

The code snippet below shows the simplest way to do this. This code uses the signals mux1 and mux2 which we defined in the last example.

However, we could easily remove the mux1 and mux2 signals from this code and instead use nested conditional operators.

This reduces the amount of code that we would have to write without affecting the functionality.

The code snippet below shows how we would do this.

As we can see from this example, when we use conditional operators to model multiplexors in verilog, the code can quickly become difficult to understand. Therefore, we should only use this method to model small multiplexors.

• Arrays as Multiplexors

It is also possible for us to use basic SystemVerilog arrays to build simple multiplexors.

In order to do this, we combine all of the multiplexor inputs into a single array type and use the address to point at an element in the array.

In order to get a better idea of how this works in practise, let's consider a basic four to one multiplexor as an example.

The first thing we must do is combine our input signals into an array. There are two ways in which we can do this.

Firstly, we can declare an array and then assign all of the individual bits, as shown in the SystemVerilog code below.

Alternatively we can use the SystemVerilog concatenation operator , which allows us to assign the entire array in one line of code.

In order to do this, we use a pair of curly braces - { } - and list the elements we wish to include in the array inside of them.

When we use the concatenation operator we can also declare and assign the variable in one statement.

The SystemVerilog code below shows how we can use the concatenation operator to populate an array.

As SystemVerilog is a loosely typed language , we can use the two bit addr signal as if it were an integer type. This signal then acts as a pointer that determines which of the four elements to select.

The code snippet below demonstrates this method in practise.

What is the difference between implicit and explicit continuous assignment?

When we use implicit continuous assignment we assign the variable a value when we declare. In contrast, when we use explicit continuous assignment we use the assign keyword to assign a value.

Write the code for a 2 to 1 multiplexor using any of the methods discussed in this post.

Write the code for circuit below using both implicit and explicit continuous assignment.

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System Verilog Operators: A Comprehensive Guide

Niranjana R

December 3, 2023

System Verilog operators : is a hardware description language used in the development and verification of digital circuits and systems. Similar to other programming languages, it has a set of operators that allow designers to perform various operations on the data. System Verilog operators are classified into different categories based on their functionality. Understanding these operators is crucial for designing efficient and error-free digital circuits.

The basic System Verilog operators include arithmetic, relational, equality, logical, bitwise, and shift operators. These operators are used to perform basic mathematical and logical operations, such as addition, subtraction, multiplication, division, and comparison, and logical operations like AND, OR, and NOT. Advanced System Verilog operators include reduction, concatenation, replication, and streaming operators. These operators are used to perform complex operations on large data sets, such as data compression, encryption, and decompression.

Table of Contents

Key Takeaways

• System Verilog operators are used in the development and verification of digital circuits and systems.
• Basic System Verilog operators include arithmetic, relational, equality, logical, bitwise, and shift operators.
• Advanced System Verilog operators include reduction, concatenation, replication, and streaming operators.

Basic System Verilog Operators

In System Verilog, operators are essential building blocks for designing digital circuits. These operators allow us to perform various operations on digital data and manipulate it to achieve the desired output. In this section, we will discuss the three basic types of operators: Arithmetic, Relational, and Logical.

Arithmetic Operators

Arithmetic operators are used to perform mathematical operations on operands. The basic arithmetic operators in System Verilog are:

For example, the expression a = b + c adds the values of b and c and stores the result in a.

Relational Operators

Relational operators are used to compare two operands. The result of a relational operator is either true or false. The relational operators in System Verilog are:

For example, the expression if (a == b) compares the values of a and b and executes the code inside the if statement if they are equal.

Logical Operators

Logical operators are used to perform logical operations on operands. The logical operators in System Verilog are:

For example, the expression if (a && b) checks if both a and b are true and executes the code inside the if statement if they are.

Understanding these basic operators is essential for designing digital circuits in System Verilog. By using these operators, we can perform various operations on digital data and manipulate it to achieve the desired output.

Advanced System Verilog Operators

In addition to the basic operators, System Verilog provides advanced operators to perform complex operations. These operators are an essential part of System Verilog and are widely used in the development of digital circuits. In this section, we will discuss two of the most important advanced operators: Bitwise Operators and Shift Operators.

Bitwise Operators

Bitwise operators are used to manipulate individual bits of a variable. System Verilog provides six bitwise operators: AND, OR, XOR, NAND, NOR, and XNOR. These operators can be used to perform various operations such as masking, setting, and clearing bits.

Shift Operators

Shift operators are used to shift the bits of a variable left or right. System Verilog provides four shift operators: left shift, right shift, arithmetic right shift, and logical right shift. These operators are used to perform various operations such as multiplication and division by powers of two.

In summary, bitwise and shift operators are essential in System Verilog for manipulating individual bits and shifting bits left or right. By using these advanced operators, we can perform complex operations with ease and efficiency.

Assignment Operators in System Verilog

In System Verilog, we use assignment operators to assign values to variables. The most commonly used assignment operator is the “=” operator. We use this operator to assign a value to a variable. For example, if we want to assign the value of 5 to a variable named “a” , we would write “a = 5;” .

System Verilog also provides us with other assignment operators that we can use to perform certain operations on variables while assigning values to them. These operators are listed in the table below:

By using these assignment operators, we can perform operations on variables and assign the result to the same variable in a single statement. This makes our code more concise and easier to read.

Conditional Operators in System Verilog

In System Verilog, conditional operators are used to create conditional expressions. They are a shorthand way to write if/else statements. The conditional operator is also known as the ternary operator because it takes three operands. The syntax of the conditional operator is as follows:

The conditional operator evaluates the condition first. If the condition is true, it evaluates the expression immediately after the question mark. If the condition is false, it evaluates the expression immediately after the colon.

One of the advantages of using the conditional operator is that it makes the code more concise and easier to read. It can also be used in assignments, which can help reduce the number of lines of code.

Another conditional operator in System Verilog is the implication operator. The implication operator is used to create logical implications. It takes two operands and returns a Boolean value. The syntax of the implication operator is as follows:

The implication operator returns true if the condition is false or if both the condition and the expression are true. It returns false if the condition is true and the expression is false.

In summary, System Verilog provides two types of conditional operators: the conditional operator and the implication operator. These operators can help reduce the number of lines of code and make the code more concise and easier to read.

Miscellaneous Operators in System Verilog

In addition to the basic arithmetic, relational, and logical operators, System Verilog provides several miscellaneous operators that can be used in digital circuit design.

Replication Operator

The replication operator {} is used to replicate a single value or a set of values multiple times. The syntax for the replication operator is {N{value}}, where N is the number of times the value is replicated.

For example, {8{1’b0}} represents a vector of eight bits, all set to 0. This operator is useful when designing circuits that require a large number of identical components.

Concatenation Operator

The concatenation operator {} is used to concatenate two or more vectors into a single vector. The syntax for the concatenation operator is {vector1, vector2, …, vectorN}, where vector1 through vectorN are the vectors being concatenated.

For example, {a, b} represents a vector that is the concatenation of vectors a and b. This operator is useful when designing circuits that require combining multiple vectors into a single vector.

Ternary Operator

The ternary operator ?: is a conditional operator that is used to assign a value to a variable based on a condition. The syntax for the ternary operator is condition ? true_value : false_value, where condition is the condition being evaluated, true_value is the value assigned if the condition is true, and false_value is the value assigned if the condition is false.

For example, y = (x>0) ? 1 : 0 assigns the value 1 to y if x is greater than 0, and assigns the value 0 to y if x is less than or equal to 0. This operator is useful when designing circuits that require conditional assignments.

Bit-select and Part-select Operators

The bit-select operator [] and the part-select operator [start:end] are used to select a single bit or a range of bits from a vector, respectively. The syntax for the bit-select operator is vector[index], where vector is the vector being selected from and index is the index of the bit being selected. The syntax for the part-select operator is vector[start:end], where vector is the vector being selected from, start is the index of the starting bit, and end is the index of the ending bit.

For example, a[7:0] represents a vector that consists of the eight least significant bits of vector a. This operator is useful when designing circuits that require selecting specific bits or ranges of bits from a vector.

These operators, along with the basic operators, provide a powerful set of tools for designing digital circuits using System Verilog.

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Tutorials in Verilog & SystemVerilog:

Examples of Resets, Mux/Demux, Rise/Fall Edge Detect, Queue, FIFO, Interface, Clocking block, Operator, clock-divider, Assertions, Power gating & Adders.

Operator usage in SystemVerilog:

• Assign operator : blocking and used in writing Combinational logic.
• Arithmetic & Assignment operator : Generally used in combinational loops , generate loops in sequential logic.
• Reduction Operators : Generally, used in combinational control logic:
• Relational Operators : Used for comparison in combinational logic:
• Shift Operators : Logical Shift & Arithmetic Shift.
• Conditional Operator : Used in combinational logic to create Muxes and/or decoder logic.
• Concatenation & Replication Operator : Used in joining bits to create Bus, concatenation can be on LHS and RHS of assignments. concatenation is treated as packed vector.
• Logical Operator : Used in comparison of logical expressions. Mainly used to compare and create boolean results. i.e True or false. Arithmetic operators are used if multiple bits are being manipulated.
• Wildcard Operator : ‘==?’, ‘!=?’. Here operator ‘?’ acts as a wildcard and matches ‘x’ and ‘z’ values from RHS to any value of corresponding bit on LHS.
• Streaming Operator : Streaming operator ‘<<‘ & ‘>>’ are used to pack or unpack the data in specified order. The packing or unpacking can be done on a matching data-type or by type-casting to a particular data-type that match the Widths. If the packed data consists of 4-State type of variable & 2-State type of variable, the result is inferred as 4-state type.

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2 thoughts on “Operator usage in SystemVerilog:”

In the example Conditional Operator: logic a, b, c, d; assign c = b ? a : d; // check if b is true if yes, then c = b else c = d. Seems that there is an error Should be // check if b is true if yes, then c = a else c = d. // The error in the given example: // c = a, not c = b

Yes. It should c = a and c = d. Thank you for pointing it out.

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• First Online: 07 July 2021

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• Ashok B. Mehta 2  

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This chapter describes all available operators of the language, including assignment, increment/decrement, arithmetic, relational, equality, logical, bitwise, shift, conditional, concatenation, replication, streaming, wildcard equality, unary reduction, etc. operators.

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52197 - Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Operators

Sep 23, 2021 • knowledge, information.

This answer record describes SystemVerilog Operators supported by Vivado Synthesis and also provides coding examples for them. The coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

Note : Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs demonstrated in each example.

logic log1, log2, log3; {log1, log2, log3} = 3b111; {log1, log2, log3} = {1b1, 1b1, 1b1}; // same effect as 3b111

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Verilog Conditional Operator

Just what the heck is that question mark doing.

Have you ever come across a strange looking piece of Verilog code that has a question mark in the middle of it? A question mark in the middle of a line of code looks so bizarre; they’re supposed to go at the end of sentences! However in Verilog the ? operator is a very useful one, but it does take a bit of getting used to.

The question mark is known in Verilog as a conditional operator though in other programming languages it also is referred to as a ternary operator , an inline if , or a ternary if . It is used as a short-hand way to write a conditional expression in Verilog (rather than using if/else statements). Let’s look at how it is used:

Here, condition is the check that the code is performing. This condition might be things like, “Is the value in A greater than the value in B?” or “Is A=1?”. Depending on if this condition evaluates to true, the first expression is chosen. If the condition evaluates to false, the part after the colon is chosen. I wrote an example of this. The code below is really elegant stuff. The way I look at the question mark operator is I say to myself, “Tell me about the value in r_Check. If it’s true, then return “HI THERE” if it’s false, then return “POTATO”. You can also use the conditional operator to assign signals , as shown with the signal w_Test1 in the example below. Assigning signals with the conditional operator is useful!

Nested Conditional Operators

There are examples in which it might be useful to combine two or more conditional operators in a single assignment. Consider the truth table below. The truth table shows a 2-input truth table. You need to know the value of both r_Sel[1] and r_Sel[0] to determine the value of the output w_Out. This could be achieved with a bunch of if-else if-else if combinations, or a case statement, but it’s much cleaner and simpler to use the conditional operator to achieve the same goal.

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