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FPGA Architecture: Principles and Progression

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Current trends and future directions in security of fpga applications with focus on thin clients.

Cameron Collins, University of Wisconsin – Green Bay and Ankur Chattopadhyay, Northern Kentucky University

1. Introduction

Recent high-profile security flaws in conventional desktop and server processors have brought increased interest and attention to the risks posed by proprietary hardware and the closely guarded, obfuscated firmware that tends to accompany it. 1 Adoption of open-source hardware and firmware could potentially address this issue. However, bringing any hardware based intellectual property (IP) to production through traditional methods may affect people plus organizations and may involve legal implications within the product’s supply chain. 2 Additionally, a large attack surface poses a problem. Field-programmable gate arrays (FPGAs) can prospectively address this concern, as they can be programmed and functionally verified directly by organizations which use them.

It can be argued that performance constraints, like speed, make FPGA-based systems a questionable substitute for the fast, integrated processors and system-on-chips used in traditional endpoint devices, but functionalities related to the core FPGA IP can be implemented in a GUI based thin client. Hence, a GUI based thin client, which can simulate the core FPGA functional logic, can be utilized as a safer i.e., a less risky, option to use with current systems, because it has lesser strings attached, as it does not involve hardware or a sizeable attack surface, and helps counter the FPGA overhead. This article seeks to explore current FPGA-ready applications and discusses future directions and potential opportunities, where FPGA can be securely implemented, i.e., simulated via a SPICE thin client, which is a modern remote desktop protocol. 3 To begin with, we next discuss some security components associated with FPGA.

Cryptography, video operations and networking are security related elements that form sound use cases for FPGAs. They benefit from the isolation and platform assurance that FPGAs offer. As a means of ensuring confidentiality and integrity of the communications between client and server, cryptographic processing applied in FPGA applications offers additional protection. Next, rendering and video decoding not only constitute a major part of a thin client’s computational workload, but are also security-critical functions. A compromised video decoding in a display system could be used to capture sensitive information from the screen or trick the users into actions that would benefit the attacker. Lastly, networking components are important to security as well. The networking stack is the first attack surface that a remote adversary will encounter during an attempted intrusion. It is also the last and only barrier to deal with in the path to data exfiltration.

2. The SPICE Protocol Features

As a newer offering, the SPICE protocol contains several convenient features that enable its usage in a modern enterprise setting. For example, the reference server implementation is designed for use with solutions, such as QEMU, 3 allowing it to be easily integrated into a desktop virtualization stack. It also supports multiple displays along with USB, audio, and smartcard redirection. It can heuristically identify areas of the screen on which videos are being displayed and apply bandwidth-efficient lossy compression to them, thereby reducing the load upon networking resources required to preserve a given framerate during multimedia consumption.

Finally, SPICE is an open source, commercially backed, and actively maintained project. However, some of its design goals may complicate attempts to build a thin client that relies on FPGAs. For instance, its creators have sought to offload most of the intensive CPU and GPU tasks to the client. To this end, the client is charged with reconstructing the complete screen from images that may be transmitted in a variety of ways via 2D vector graphics primitives. 4 This helps avoid the need of more powerful FPGA hardware and more complex graphics IP cores for speedy rendering in a thin client where SPICE is used.

3. Benefits of FPGA in a SPICE Thin Client

Several functions in SPICE can be relocated to special-purpose coprocessors implemented on FPGAs. Such an approach has a variety of potential benefits. For instance, it would help isolate security-critical functions from each other as well as any buggy, vulnerable, or untrusted software that might be running on the general-purpose processor. It may also help reduce the impact that semiconductor product lifecycles may have on the thin client’s service lifespan. The use of FPGA-compatible soft cores to replace out-of-production semiconductor components has already been studied. 5 It may be easier for large-volume customers to negotiate for extended production of one FPGA than several discrete components. When the chosen FPGA is no longer manufactured, a pin-compatible successor may well be available. If an IP core contains fundamental security flaws, then it can be replaced through enough resources by a comparable alternative without requiring changes to physical hardware. The configuration of a device’s FPGA(s) could be updated in the field, if a secure mechanism for doing so is provided.

4. SPICE FPGA: Security Angles and Future Work 

FPGA-ready hardware implementations of cryptosystems, including AES 6, 7, 8 and RSA 9, 10 are used to authenticate the client with the server in SPICE. x22519, as used in elliptic curve Diffie-Hellman key exchanges, have been also used in this regard by researchers. 11 AES can be used as part of the networking stack in a Wi-Fi capable thin client. RSA and x22519 can be employed by Transport Layer Services (TLS), which is supported by the SPICE server for securing communication channels. 9, 11

SPICE can use multiple methods to send video from server to client. The server transmits areas of the display determined to contain video as MJPEG streams to save bandwidth. 12 Several FPGA-based JPEG decoders have been demonstrated by researchers. 13 Even early designs proved capable of processing 30 frames per second on then-current hardware. As MJPEG streams consist simply of a sequence of separately encoded JPEG images, these JPEG decoders might be good candidates for adaption to MJPEG. Other parts of the screen may be sent as images compressed by one of the following lossless algorithms, namely QUIC, which is a “global” extension of LZ and is specific to SPICE, or LZSS. 14 Researchers have successfully implemented a decompressor for DEFLATE, 15 which incorporates LZSS on an FPGA, and can be supported.

Image decoding or decompression on FPGAs has been explored, and SPICE allows parts of the frame to be reproduced by 2D vector graphics commands. For instance, text and primitive shapes can be rendered directly on the client rather than being transmitted as an image. In this context, a SPICE client may be served by Cairo, a sizable graphics library. Vector graphics rasterizers have been created for FPGAs, 4 but whether their capabilities meet the requirements of the SPICE protocol remains an open research question.

5. Summary 

Overall, the SPICE protocol, as discussed in this article, can be potentially used as a thin client with FPGA applications, i.e., as a SPICE FPGA for an overall more optimal, secure and practical implementation. However, as discussed and pointed out in this article, there are a few specific aspects of this usage of a thin client with FPGAs that need to be explored in detail as part of future research. Also, another scope of future work is to compare the performance of SPICE with that of other available thin clients, which can be used with FPGA applications.

References 

• V. Narayanan, M. S. Baranowski, L. Ryzhyk, Z. Rakamarić, and A. Burtsev, “RedLeaf: Towards An Operating System for Safe and Verified Firmware,” HotOS 2019 , 2019.
• S. Ray, E. Peeters, M. M. Tehranipoor and S. Bhunia, “System-on-Chip Platform Security Assurance: Architecture and Validation,” in Proceedings of the IEEE , vol. 106, no. 1, pp. 21-37, Jan. 2018. doi: 10.1109/JPROC.2017.2714641.
• “ Home ,” SPICE . [Online] [Accessed: 10-Nov-2019].
• S. G. Ramanathan, B. P. Kumar, C. M. Ananda and E. P. Jayakumar, “Design of graphics processing framework on FPGA,” 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) , Bangalore, 2016, pp. 387-391. doi: 10.1109/RTEICT.2016.7807847.
• Z. Zhang, L. Njilla, C. Kamhoua, K. Kwiat and Q. Yu, “Securing FPGA-based obsolete component replacement for legacy systems,” 2018 19th International Symposium on Quality Electronic Design (ISQED) , Santa Clara, CA, 2018, pp. 401-406. doi: 10.1109/ISQED.2018.8357320.
• M. Rao, A. Kaknjo, E. Omerdic, D. Toal and T. Newe, “An Efficient High Speed AES Implementation Using Traditional FPGA and LabVIEW FPGA Platforms,” 2018 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC) , Zhengzhou, China, 2018, pp. 93-937. doi: 10.1109/CyberC.2018.00028.
• N. Gaur, A. Mehra and P. Kumar, “Enhanced AES Architecture using Extended Set ALU at 28nm FPGA,” 2018 5th International Conference on Signal Processing and Integrated Networks (SPIN) , Noida, 2018, pp. 437-440. doi: 10.1109/SPIN.2018.8474090.
• S. U. Jonwal and P. P. Shingare, “Advanced Encryption Standard (AES) implementation on FPGA with hardware in loop,” 2017 International Conference on Trends in Electronics and Informatics (ICEI) , Tirunelveli, 2017, pp. 64-67, doi: 10.1109/ICOEI.2017.8300776.
• T. Isobe, S. Tsutsumi, K. Seto, K. Aoshima and K. Kariya, “10 Gbps implementation of TLS/SSL accelerator on FPGA,” 2010 IEEE 18th International Workshop on Quality of Service (IWQoS) , Beijing, 2010, pp. 1-6. doi: 10.1109/IWQoS.2010.5542723.
• A. Thiruneelakandan and T. Thirumurugan, “An approach towards improved cyber security by hardware acceleration of OpenSSL cryptographic functions,” 2011 International Conference on Electronics, Communication and Computing Technologies , Pauls Nagar, 2011, pp. 13-16. doi:10.1109/ICECCT.2011.6077061.
• P. Sasdrich and T. Géneysu, “Cryptography for next generation TLS: Implementing the RFC 7748 elliptic Curve 448 cryptosystem in hardware,” 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) , Austin, TX, 2017, pp. 1-6. doi: 10.1145/3061639.3062222.
• L. Chen, N. Shashidhar and Q. Liu, “Scalable Secure MJPEG Video Streaming,” 2012 26th International Conference on Advanced Information Networking and Applications Workshops , Fukuoka, 2012, pp. 111-115. doi: 10.1109/WAINA.2012.163.
• G. Kyrtsakas and R. Muscedere, “An FPGA implementation of a custom JPEG image decoder SoC module,” 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE) , Windsor, ON, 2017, pp. 1-4. doi: 10.1109/CCECE.2017.7946826.
• I. Shcherbakov, C. Weis and N. Wehn, “A High-Performance FPGA-Based Implementation of the LZSS Compression Algorithm,” 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum , Shanghai, 2012, pp. 449-453. doi: 10.1109/IPDPSW.2012.58.
• M. Ledwon, B. F. Cockburn and J. Han, “Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression,” 2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE) , Edmonton, AB, Canada, 2019, pp. 1-6. doi: 10.1109/CCECE.2019.8861851.

Cameron Collins is an undergraduate student (senior) at the University of Wisconsin at Green Bay (UWGB) pursuing a Bachelors in Computer Science with emphasis in Information Assurance and Security. His research interests focus on security issues in FPGAs, and he has worked on surveying security risks with FPGAs as part of his senior capstone research project under the supervision plus mentoring of Dr. Ankur Chattopadhyay. He has been working with the UWGB IT Support division as an employee and loves to explore IT issues as well as learn new technologies.

Dr. Ankur Chattopadhyay  earned his Ph.D. in Computer Science from the  University of Colorado at Colorado Springs (UCCS) , and is currently an Assistant Professor of Cybersecurity in the  Computer Science Department  at  Northern Kentucky University (NKU) . He joined NKU in January, 2020, and his research interests include visual privacy, visual trust, computer science & cybersecurity education, privacy-enhancing computer vision & pattern recognition, adversarial thinking & learning in machine vision, and inclusive privacy & security in visual surveillance. He is currently an Editorial Board Member with the  IEEE Future Directions Newsletter in Technology, Policy and Ethics . He is an active professional member of  IEEE  and  ACM . He has over 30 peer-reviewed publications, including conference papers, newsletter articles and journal papers. He has more than 15 years of work experience in both academics and industry. Ankur is originally from  Kolkata, India , where he did his Bachelors in Computer Engineering from the  Institute of Engineering & Management (IEM) , and was employed with  Tata Consultancy Services , a global computer consultancy firm, for almost 7 years. Before joining NKU, he was an Assistant Professor of Computer Science at the  University of Wisconsin – Green Bay (UWGB) , where he founded and directed of the Center of Cybersecurity Education & Outreach. He was the principal investigator (PI) and the project director of the first-ever  NSA/NSF GenCyber  program in the state of Wisconsin at UWGB, where he has led and hosted the GenCyber program for three years. He has also worked with Google and Microsoft as the PI/project lead for the Google IgniteCS and Microsoft TechSpark grant programs at UWGB. His industry profile includes multiple roles like IT Analyst, Software Engineer and Embedded Systems Engineer.

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A Survey of FPGA-Based Deep Learning Acceleration Research

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• Ziyi Lv   ORCID: orcid.org/0000-0002-9676-7833 40 , 41 &
• Jing Zhang   ORCID: orcid.org/0000-0002-0171-0683 40 , 41  

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 813))

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In a range of fields such as emotion detection, medical image processing and speech recognition, deep learning has recently achieved good results. With the pursuit of more precise results, many scholars try to add more new type network layers to increase the size of the neural network. However, this will lead to deeper and more intricate network models, and training and evaluating models requires intensive CPU calculations and tremendous computing resources which cannot be achieved by general purpose processors. Nowadays, some hardware accelerators such as Field Programmable Gate Array (FPGA) have been employed to accelerate the neural network, and FPGA with reconfigurability and low power consumption are currently applied to improve throughput of deep learning networks at a reasonable price. In this paper, the typical technologies and methods of accelerating deep learning network on FPGA in recent years are reviewed and analyzed with their advantages and disadvantages, and feasible research suggestions for the next research direction are given. It is expected that it will have a certain reference value for researchers in the field of deep learning acceleration and hardware optimization.

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A survey of FPGA-based accelerators for convolutional neural networks

Yann, L., Yoshua, B.: Convolutional networks for images, speech, and time series. Handb. Brain Theory Neural Netw. 3361 (10) (1995)

Google Scholar  

Xingjian, S., Zhourong, C., Hao, W., et al.: Convolutional LSTM network. In: Proceedings of the 27th International Conference on Neural Information Processing Systems, A Machine Learning Approach for Precipitation Nowcasting, pp. 2672–2680. MIT Press (2015)

Ian, J.G., Jean, P.-A., Mehdi, M., et al.: Generative Adversarial Nets. MIT Press (2014)

Jiantao, Q., Song, S., Yu, W., et al.: Going deeper with embedded FPGA platform for convolutional neural network. In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 26–35. ACM (2016)

Chen, Z., Peng, L., Sun, G., et al.: Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 161–170. ACM (2015)

Williams, S., Waterman, A., Patterson, D.: Roofline: an insightful visual performance model for multicore architectures. Commun. Assoc. Comput. Mach. 52 (4), 65–76 (2009)

Xuelei, L., Liangkui, D., Li, W., Fang, C.: FPGA accelerates deep residual learning for image recognition. In: 2017 IEEE 2nd Information Technology, Networking, Electronic and Automation Control Conference (ITNEC). IEEE, Chengdu (2017)

Roberto, D., Griffin, L., Jasmina, V., Paul, C., Graham, T., Shawki, A.: Caffeinated FPGAs: FPGA framework for convolutional neural networks. In: 2016 International Conference on Field-Programmable Technology (FPT). IEEE, Xi’an (2017)

Chao, W., Junneng, Z., et al.: Hardware implementation on FPGA for task-level parallel dataflow execution engine. IEEE Trans. Parall. Distrib. Syst. 27 (8), 2303–2315 (2016)

Article   Google Scholar  

Chen, Z., Di, W., Jiayu, S., Guangyu, S., Guojie, L., Jason, C.: Energy-efficient CNN implementation on a deeply pipelined FPGA cluster. In: Proceedings of the 2016 International Symposium, pp. 326–331 (2016)

Hector A.G., Shahzad, M., Jerald, Y., Ibrahim M.E.: BioCNN: a hardware inference engine for EEG-based emotion detection. IEEE Access 140896–140914 (2020)

Lei, G., Chao, W., Xi, L., Huaping, C., Xuehai, Z.: MALOC: a fully pipelined FPGA accelerator for convolutional neural networks with all layers mapped on chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11), 2601–2612 (2018)

Ming, X., Zunkai, H., Li, T., Hui, W., Victor, C., Yongxin, Z., Songlin, F.: SparkNoC: an energy-efficiency FPGA-based accelerator using optimized lightweight CNN for edge computing. J. Syst. Archit. 115 (4), 101991 (2021)

Gan, F., Zuyi, H., Song, C., Feng, W.: Energy-efficient and high-throughput FPGA-based accelerator for Convolutional Neural Networks. In: 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, Hangzhou (2017)

Dong, W., An, J., Xu, K.: PipeCNN: an OpenCL-based FPGA accelerator for large-scale convolution neuron networks. CoRR 1611 (02450) (2016)

Kaiyuan, G., Lingzhi, S., Jiantao, Q., et al.: Angel-eye: a complete design flow for mapping CNN onto embedded FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (1), 35–47 (2017)

Liqiang, L., Yun, L., Qingcheng, X., Shengen, Y.: Evaluating fast algorithms for convolutional neural networks on FPGAs. In: 2017 IEEE 25th Annual International Symposium on Field-programmable Custom Computing Machines. IEEE, Napa (2017)

Yufei, M., Yu, C., Sarma, V., Jae-sun, S.: Optimizing the convolution operation to accelerate deep neural networks on FPGA. IEEE Trans. Very Large-Scale Integr. (VLSI) Syst. 26 (7), 1354–1367 (2018)

Lei, G., Chao, W., Xi, L., Huangping, C., Xuehai, Z.: A power-efficient and high-performance FPGA accelerator for convolutional neural networks. In: Proceedings of the 12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, pp. 1–2 (2017)

Chao, H., Siyu, N., Gengsheng, C.: A layer-based structured design of CNN on FPGA. In: 2017 IEEE 12th International Conference on ASIC (ASICON). IEEE, Guiyang (2017)

Waichi, F., Kaiyen, W., Nicolas, F., Yunlun, H., Yude, H.: Development and validation of an EEG-based real-time emotion recognition system using edge AI computing platform with convolutional neural network system-on-chip design. IEEE J. Emerg. Sel. Top. Circ. Syst. 9 (4), 645–657 (2019)

Jing, M., Chen, L., Zhiyong, G.: Hardware Implementation and optimization of tiny-YOLO network. Springer, Singapore (2017)

Ke, X., Xiaoyun, W., Dong, W.: A scalable OpenCL-based FPGA accelerator for YOLOv2. In: 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, San Diego (2019)

Hiroki, N., Masayuki, S., Shimpei, S.: A demonstration of FPGA-based you only look once version2 (YOLOv2). In: 2018 28th International Conference on Field Programmable Logic and Applications (FPL). IEEE, Dublin (2018)

Hiroki, N., Haruyoshi, Y., Tomoya, F., Shimpei, S.: A lightweight YOLOv2: a binarized CNN with a parallel support vector regression for an FPGA. In: Proceedings of the 2018 ACM/SIGDA International Symposium, pp. 31–40. ACM (2018)

Chaoyang, Z., Kejie, H., Shuyuan, Y., Ziqi, Z., Hejia, Z., Haibin, S.: An efficient hardware accelerator for structured sparse convolutional neural networks on FPGAs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 1–13 (2020)

Zixiao, W., Ke, X., Shuaixiao, W., Li, Liu., Lingzhi, L., Dong, W.: Sparse-YOLO: hardware/software co-design of an FPGA accelerator for YOLOv2. IEEE Access 8 (99), 116569–116585 (2020)

Xianchao, X., Brian, L.: FCLNN: a flexible framework for fast CNN prototyping on FPGA with OpenCL and Caffe. In: 2018 International Conference on Field-Programmable Technology (FPT). IEEE, Naha (2018)

Caiwen, D., Shuo, W., Ning, L., Kaidi, X., Yanzhi, W., Yun, L.: REQ-YOLO: a resource-aware, efficient quantization framework for object detection on FPGAs. In: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 33–42 (2019)

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Acknowledgements

This research is supported by: (1) 2020-2022 National Natural Science Foundation of China under Grand (Youth) No. 52001039 (2) 2020-2022 Funding of Shandong Natural Science Foundation in China No. ZR2019LZH005.

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Lv, Z., Zhang, J. (2022). A Survey of FPGA-Based Deep Learning Acceleration Research. In: Yao, J., Xiao, Y., You, P., Sun, G. (eds) The International Conference on Image, Vision and Intelligent Systems (ICIVIS 2021). Lecture Notes in Electrical Engineering, vol 813. Springer, Singapore. https://doi.org/10.1007/978-981-16-6963-7_5

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